6602 lines
247 KiB
Plaintext
6602 lines
247 KiB
Plaintext
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Open_Box.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 00000188 08000000 08000000 00010000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00002adc 08000188 08000188 00010188 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000030 08002c64 08002c64 00012c64 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08002c94 08002c94 0002000c 2**0
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CONTENTS
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4 .ARM 00000000 08002c94 08002c94 0002000c 2**0
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CONTENTS
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5 .preinit_array 00000000 08002c94 08002c94 0002000c 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08002c94 08002c94 00012c94 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 .fini_array 00000004 08002c98 08002c98 00012c98 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .data 0000000c 20000000 08002c9c 00020000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 0000006c 2000000c 08002ca8 0002000c 2**2
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ALLOC
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10 ._user_heap_stack 00000600 20000078 08002ca8 00020078 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 0002000c 2**0
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CONTENTS, READONLY
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12 .debug_info 00008dea 00000000 00000000 0002003c 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 0000141e 00000000 00000000 00028e26 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00000940 00000000 00000000 0002a248 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_ranges 00000898 00000000 00000000 0002ab88 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 0001a2ca 00000000 00000000 0002b420 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 0000a514 00000000 00000000 000456ea 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 0009d709 00000000 00000000 0004fbfe 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000050 00000000 00000000 000ed307 2**0
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CONTENTS, READONLY
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20 .debug_frame 00002660 00000000 00000000 000ed358 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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08000188 <__do_global_dtors_aux>:
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8000188: b510 push {r4, lr}
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800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>)
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800018c: 7823 ldrb r3, [r4, #0]
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800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
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8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>)
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8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
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8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>)
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8000196: f3af 8000 nop.w
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800019a: 2301 movs r3, #1
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800019c: 7023 strb r3, [r4, #0]
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800019e: bd10 pop {r4, pc}
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80001a0: 2000000c .word 0x2000000c
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80001a4: 00000000 .word 0x00000000
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80001a8: 08002c4c .word 0x08002c4c
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080001ac <frame_dummy>:
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80001ac: b508 push {r3, lr}
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80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc <frame_dummy+0x10>)
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80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
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80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 <frame_dummy+0x14>)
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80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 <frame_dummy+0x18>)
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80001b6: f3af 8000 nop.w
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80001ba: bd08 pop {r3, pc}
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80001bc: 00000000 .word 0x00000000
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80001c0: 20000010 .word 0x20000010
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80001c4: 08002c4c .word 0x08002c4c
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080001c8 <main>:
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/**
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* @brief The application entry point.
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* @retval int
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*/
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int main(void)
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{
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80001c8: b580 push {r7, lr}
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80001ca: af00 add r7, sp, #0
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/* USER CODE END 1 */
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/* MCU Configuration--------------------------------------------------------*/
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/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
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HAL_Init();
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80001cc: f000 f9f4 bl 80005b8 <HAL_Init>
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/* USER CODE BEGIN Init */
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/* USER CODE END Init */
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/* Configure the system clock */
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SystemClock_Config();
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80001d0: f000 f836 bl 8000240 <SystemClock_Config>
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/* USER CODE BEGIN SysInit */
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/* USER CODE END SysInit */
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/* Initialize all configured peripherals */
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MX_GPIO_Init();
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80001d4: f000 f8d2 bl 800037c <MX_GPIO_Init>
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MX_TIM2_Init();
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80001d8: f000 f874 bl 80002c4 <MX_TIM2_Init>
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/* USER CODE BEGIN 2 */
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HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_2);
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80001dc: 2104 movs r1, #4
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80001de: 4817 ldr r0, [pc, #92] ; (800023c <main+0x74>)
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80001e0: f001 ff62 bl 80020a8 <HAL_TIM_PWM_Start>
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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while (1)
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{
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if(HAL_GPIO_ReadPin(Sens1_GPIO_Port, Sens1_Pin) == GPIO_PIN_SET)
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80001e4: 2120 movs r1, #32
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80001e6: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
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80001ea: f000 fcc7 bl 8000b7c <HAL_GPIO_ReadPin>
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80001ee: 4603 mov r3, r0
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80001f0: 2b01 cmp r3, #1
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80001f2: d104 bne.n 80001fe <main+0x36>
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{
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__HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_2, 8000);
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80001f4: 4b11 ldr r3, [pc, #68] ; (800023c <main+0x74>)
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80001f6: 681b ldr r3, [r3, #0]
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80001f8: f44f 52fa mov.w r2, #8000 ; 0x1f40
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80001fc: 639a str r2, [r3, #56] ; 0x38
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}
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if(HAL_GPIO_ReadPin(Sens2_GPIO_Port, Sens2_Pin) == GPIO_PIN_SET)
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80001fe: 2110 movs r1, #16
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8000200: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
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8000204: f000 fcba bl 8000b7c <HAL_GPIO_ReadPin>
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8000208: 4603 mov r3, r0
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800020a: 2b01 cmp r3, #1
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800020c: d104 bne.n 8000218 <main+0x50>
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{
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__HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_2, 16000);
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800020e: 4b0b ldr r3, [pc, #44] ; (800023c <main+0x74>)
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8000210: 681b ldr r3, [r3, #0]
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8000212: f44f 527a mov.w r2, #16000 ; 0x3e80
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8000216: 639a str r2, [r3, #56] ; 0x38
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}
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HAL_Delay(2000);
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8000218: f44f 60fa mov.w r0, #2000 ; 0x7d0
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800021c: f000 fa32 bl 8000684 <HAL_Delay>
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HAL_GPIO_WritePin(Ctr_Vin1_GPIO_Port, Ctr_Vin1_Pin, GPIO_PIN_RESET);
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8000220: 2200 movs r2, #0
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8000222: 2140 movs r1, #64 ; 0x40
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8000224: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
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8000228: f000 fcc0 bl 8000bac <HAL_GPIO_WritePin>
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HAL_GPIO_WritePin(Ctr_Vin2_GPIO_Port, Ctr_Vin2_Pin, GPIO_PIN_RESET);
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800022c: 2200 movs r2, #0
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800022e: 2108 movs r1, #8
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8000230: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
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8000234: f000 fcba bl 8000bac <HAL_GPIO_WritePin>
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if(HAL_GPIO_ReadPin(Sens1_GPIO_Port, Sens1_Pin) == GPIO_PIN_SET)
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8000238: e7d4 b.n 80001e4 <main+0x1c>
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800023a: bf00 nop
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800023c: 20000028 .word 0x20000028
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08000240 <SystemClock_Config>:
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/**
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* @brief System Clock Configuration
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* @retval None
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*/
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void SystemClock_Config(void)
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{
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8000240: b580 push {r7, lr}
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8000242: b090 sub sp, #64 ; 0x40
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8000244: af00 add r7, sp, #0
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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8000246: f107 0318 add.w r3, r7, #24
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800024a: 2228 movs r2, #40 ; 0x28
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800024c: 2100 movs r1, #0
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800024e: 4618 mov r0, r3
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8000250: f002 fcf4 bl 8002c3c <memset>
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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8000254: 1d3b adds r3, r7, #4
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8000256: 2200 movs r2, #0
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8000258: 601a str r2, [r3, #0]
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800025a: 605a str r2, [r3, #4]
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800025c: 609a str r2, [r3, #8]
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800025e: 60da str r2, [r3, #12]
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8000260: 611a str r2, [r3, #16]
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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8000262: 2302 movs r3, #2
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8000264: 61bb str r3, [r7, #24]
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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8000266: 2301 movs r3, #1
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8000268: 62bb str r3, [r7, #40] ; 0x28
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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800026a: 2310 movs r3, #16
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800026c: 62fb str r3, [r7, #44] ; 0x2c
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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800026e: 2302 movs r3, #2
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8000270: 637b str r3, [r7, #52] ; 0x34
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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8000272: 2300 movs r3, #0
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8000274: 63bb str r3, [r7, #56] ; 0x38
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RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
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8000276: f44f 2300 mov.w r3, #524288 ; 0x80000
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800027a: 63fb str r3, [r7, #60] ; 0x3c
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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800027c: f107 0318 add.w r3, r7, #24
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8000280: 4618 mov r0, r3
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8000282: f000 fcab bl 8000bdc <HAL_RCC_OscConfig>
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8000286: 4603 mov r3, r0
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8000288: 2b00 cmp r3, #0
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800028a: d001 beq.n 8000290 <SystemClock_Config+0x50>
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{
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Error_Handler();
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800028c: f000 f8b2 bl 80003f4 <Error_Handler>
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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8000290: 230f movs r3, #15
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8000292: 607b str r3, [r7, #4]
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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8000294: 2302 movs r3, #2
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8000296: 60bb str r3, [r7, #8]
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
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8000298: 2380 movs r3, #128 ; 0x80
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800029a: 60fb str r3, [r7, #12]
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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800029c: f44f 6380 mov.w r3, #1024 ; 0x400
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80002a0: 613b str r3, [r7, #16]
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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80002a2: 2300 movs r3, #0
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80002a4: 617b str r3, [r7, #20]
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
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80002a6: 1d3b adds r3, r7, #4
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80002a8: 2100 movs r1, #0
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80002aa: 4618 mov r0, r3
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80002ac: f001 fcd4 bl 8001c58 <HAL_RCC_ClockConfig>
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80002b0: 4603 mov r3, r0
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80002b2: 2b00 cmp r3, #0
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80002b4: d001 beq.n 80002ba <SystemClock_Config+0x7a>
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{
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Error_Handler();
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80002b6: f000 f89d bl 80003f4 <Error_Handler>
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}
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}
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80002ba: bf00 nop
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80002bc: 3740 adds r7, #64 ; 0x40
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80002be: 46bd mov sp, r7
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80002c0: bd80 pop {r7, pc}
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...
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080002c4 <MX_TIM2_Init>:
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* @brief TIM2 Initialization Function
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* @param None
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* @retval None
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*/
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static void MX_TIM2_Init(void)
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{
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80002c4: b580 push {r7, lr}
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80002c6: b08a sub sp, #40 ; 0x28
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80002c8: af00 add r7, sp, #0
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/* USER CODE BEGIN TIM2_Init 0 */
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/* USER CODE END TIM2_Init 0 */
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TIM_MasterConfigTypeDef sMasterConfig = {0};
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80002ca: f107 031c add.w r3, r7, #28
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80002ce: 2200 movs r2, #0
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80002d0: 601a str r2, [r3, #0]
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80002d2: 605a str r2, [r3, #4]
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80002d4: 609a str r2, [r3, #8]
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TIM_OC_InitTypeDef sConfigOC = {0};
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80002d6: 463b mov r3, r7
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80002d8: 2200 movs r2, #0
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80002da: 601a str r2, [r3, #0]
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80002dc: 605a str r2, [r3, #4]
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80002de: 609a str r2, [r3, #8]
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80002e0: 60da str r2, [r3, #12]
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80002e2: 611a str r2, [r3, #16]
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80002e4: 615a str r2, [r3, #20]
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80002e6: 619a str r2, [r3, #24]
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/* USER CODE BEGIN TIM2_Init 1 */
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/* USER CODE END TIM2_Init 1 */
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htim2.Instance = TIM2;
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80002e8: 4b22 ldr r3, [pc, #136] ; (8000374 <MX_TIM2_Init+0xb0>)
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80002ea: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
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80002ee: 601a str r2, [r3, #0]
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htim2.Init.Prescaler = 0;
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80002f0: 4b20 ldr r3, [pc, #128] ; (8000374 <MX_TIM2_Init+0xb0>)
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80002f2: 2200 movs r2, #0
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80002f4: 605a str r2, [r3, #4]
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htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
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80002f6: 4b1f ldr r3, [pc, #124] ; (8000374 <MX_TIM2_Init+0xb0>)
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80002f8: 2200 movs r2, #0
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80002fa: 609a str r2, [r3, #8]
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htim2.Init.Period = 159999;
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80002fc: 4b1d ldr r3, [pc, #116] ; (8000374 <MX_TIM2_Init+0xb0>)
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80002fe: 4a1e ldr r2, [pc, #120] ; (8000378 <MX_TIM2_Init+0xb4>)
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8000300: 60da str r2, [r3, #12]
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htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
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8000302: 4b1c ldr r3, [pc, #112] ; (8000374 <MX_TIM2_Init+0xb0>)
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8000304: 2200 movs r2, #0
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8000306: 611a str r2, [r3, #16]
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htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
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8000308: 4b1a ldr r3, [pc, #104] ; (8000374 <MX_TIM2_Init+0xb0>)
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800030a: 2200 movs r2, #0
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800030c: 619a str r2, [r3, #24]
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if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
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800030e: 4819 ldr r0, [pc, #100] ; (8000374 <MX_TIM2_Init+0xb0>)
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8000310: f001 fe72 bl 8001ff8 <HAL_TIM_PWM_Init>
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8000314: 4603 mov r3, r0
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8000316: 2b00 cmp r3, #0
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8000318: d001 beq.n 800031e <MX_TIM2_Init+0x5a>
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{
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Error_Handler();
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800031a: f000 f86b bl 80003f4 <Error_Handler>
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}
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sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
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800031e: 2300 movs r3, #0
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8000320: 61fb str r3, [r7, #28]
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sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
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8000322: 2300 movs r3, #0
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8000324: 627b str r3, [r7, #36] ; 0x24
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if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
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8000326: f107 031c add.w r3, r7, #28
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800032a: 4619 mov r1, r3
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800032c: 4811 ldr r0, [pc, #68] ; (8000374 <MX_TIM2_Init+0xb0>)
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800032e: f002 fbfb bl 8002b28 <HAL_TIMEx_MasterConfigSynchronization>
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8000332: 4603 mov r3, r0
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8000334: 2b00 cmp r3, #0
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8000336: d001 beq.n 800033c <MX_TIM2_Init+0x78>
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{
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Error_Handler();
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8000338: f000 f85c bl 80003f4 <Error_Handler>
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}
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sConfigOC.OCMode = TIM_OCMODE_PWM1;
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800033c: 2360 movs r3, #96 ; 0x60
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800033e: 603b str r3, [r7, #0]
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sConfigOC.Pulse = 8000;
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8000340: f44f 53fa mov.w r3, #8000 ; 0x1f40
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8000344: 607b str r3, [r7, #4]
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sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
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8000346: 2300 movs r3, #0
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8000348: 60bb str r3, [r7, #8]
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sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
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800034a: 2300 movs r3, #0
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800034c: 613b str r3, [r7, #16]
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if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
|
|
800034e: 463b mov r3, r7
|
|
8000350: 2204 movs r2, #4
|
|
8000352: 4619 mov r1, r3
|
|
8000354: 4807 ldr r0, [pc, #28] ; (8000374 <MX_TIM2_Init+0xb0>)
|
|
8000356: f001 ff8d bl 8002274 <HAL_TIM_PWM_ConfigChannel>
|
|
800035a: 4603 mov r3, r0
|
|
800035c: 2b00 cmp r3, #0
|
|
800035e: d001 beq.n 8000364 <MX_TIM2_Init+0xa0>
|
|
{
|
|
Error_Handler();
|
|
8000360: f000 f848 bl 80003f4 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM2_Init 2 */
|
|
|
|
/* USER CODE END TIM2_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim2);
|
|
8000364: 4803 ldr r0, [pc, #12] ; (8000374 <MX_TIM2_Init+0xb0>)
|
|
8000366: f000 f88d bl 8000484 <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
800036a: bf00 nop
|
|
800036c: 3728 adds r7, #40 ; 0x28
|
|
800036e: 46bd mov sp, r7
|
|
8000370: bd80 pop {r7, pc}
|
|
8000372: bf00 nop
|
|
8000374: 20000028 .word 0x20000028
|
|
8000378: 000270ff .word 0x000270ff
|
|
|
|
0800037c <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
800037c: b580 push {r7, lr}
|
|
800037e: b086 sub sp, #24
|
|
8000380: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000382: 1d3b adds r3, r7, #4
|
|
8000384: 2200 movs r2, #0
|
|
8000386: 601a str r2, [r3, #0]
|
|
8000388: 605a str r2, [r3, #4]
|
|
800038a: 609a str r2, [r3, #8]
|
|
800038c: 60da str r2, [r3, #12]
|
|
800038e: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000390: 4b17 ldr r3, [pc, #92] ; (80003f0 <MX_GPIO_Init+0x74>)
|
|
8000392: 695b ldr r3, [r3, #20]
|
|
8000394: 4a16 ldr r2, [pc, #88] ; (80003f0 <MX_GPIO_Init+0x74>)
|
|
8000396: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
|
800039a: 6153 str r3, [r2, #20]
|
|
800039c: 4b14 ldr r3, [pc, #80] ; (80003f0 <MX_GPIO_Init+0x74>)
|
|
800039e: 695b ldr r3, [r3, #20]
|
|
80003a0: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
80003a4: 603b str r3, [r7, #0]
|
|
80003a6: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOA, Ctr_Vin2_Pin|Ctr_Vin1_Pin, GPIO_PIN_SET);
|
|
80003a8: 2201 movs r2, #1
|
|
80003aa: 2148 movs r1, #72 ; 0x48
|
|
80003ac: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
80003b0: f000 fbfc bl 8000bac <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : Ctr_Vin2_Pin Ctr_Vin1_Pin */
|
|
GPIO_InitStruct.Pin = Ctr_Vin2_Pin|Ctr_Vin1_Pin;
|
|
80003b4: 2348 movs r3, #72 ; 0x48
|
|
80003b6: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80003b8: 2301 movs r3, #1
|
|
80003ba: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80003bc: 2300 movs r3, #0
|
|
80003be: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80003c0: 2300 movs r3, #0
|
|
80003c2: 613b str r3, [r7, #16]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80003c4: 1d3b adds r3, r7, #4
|
|
80003c6: 4619 mov r1, r3
|
|
80003c8: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
80003cc: f000 fa64 bl 8000898 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : Sens2_Pin Sens1_Pin */
|
|
GPIO_InitStruct.Pin = Sens2_Pin|Sens1_Pin;
|
|
80003d0: 2330 movs r3, #48 ; 0x30
|
|
80003d2: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
80003d4: 2300 movs r3, #0
|
|
80003d6: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
80003d8: 2302 movs r3, #2
|
|
80003da: 60fb str r3, [r7, #12]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80003dc: 1d3b adds r3, r7, #4
|
|
80003de: 4619 mov r1, r3
|
|
80003e0: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
80003e4: f000 fa58 bl 8000898 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
80003e8: bf00 nop
|
|
80003ea: 3718 adds r7, #24
|
|
80003ec: 46bd mov sp, r7
|
|
80003ee: bd80 pop {r7, pc}
|
|
80003f0: 40021000 .word 0x40021000
|
|
|
|
080003f4 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
80003f4: b480 push {r7}
|
|
80003f6: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80003f8: b672 cpsid i
|
|
}
|
|
80003fa: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
80003fc: e7fe b.n 80003fc <Error_Handler+0x8>
|
|
...
|
|
|
|
08000400 <HAL_MspInit>:
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8000400: b480 push {r7}
|
|
8000402: b083 sub sp, #12
|
|
8000404: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8000406: 4b0f ldr r3, [pc, #60] ; (8000444 <HAL_MspInit+0x44>)
|
|
8000408: 699b ldr r3, [r3, #24]
|
|
800040a: 4a0e ldr r2, [pc, #56] ; (8000444 <HAL_MspInit+0x44>)
|
|
800040c: f043 0301 orr.w r3, r3, #1
|
|
8000410: 6193 str r3, [r2, #24]
|
|
8000412: 4b0c ldr r3, [pc, #48] ; (8000444 <HAL_MspInit+0x44>)
|
|
8000414: 699b ldr r3, [r3, #24]
|
|
8000416: f003 0301 and.w r3, r3, #1
|
|
800041a: 607b str r3, [r7, #4]
|
|
800041c: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800041e: 4b09 ldr r3, [pc, #36] ; (8000444 <HAL_MspInit+0x44>)
|
|
8000420: 69db ldr r3, [r3, #28]
|
|
8000422: 4a08 ldr r2, [pc, #32] ; (8000444 <HAL_MspInit+0x44>)
|
|
8000424: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
8000428: 61d3 str r3, [r2, #28]
|
|
800042a: 4b06 ldr r3, [pc, #24] ; (8000444 <HAL_MspInit+0x44>)
|
|
800042c: 69db ldr r3, [r3, #28]
|
|
800042e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8000432: 603b str r3, [r7, #0]
|
|
8000434: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8000436: bf00 nop
|
|
8000438: 370c adds r7, #12
|
|
800043a: 46bd mov sp, r7
|
|
800043c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000440: 4770 bx lr
|
|
8000442: bf00 nop
|
|
8000444: 40021000 .word 0x40021000
|
|
|
|
08000448 <HAL_TIM_PWM_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_pwm: TIM_PWM handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
|
|
{
|
|
8000448: b480 push {r7}
|
|
800044a: b085 sub sp, #20
|
|
800044c: af00 add r7, sp, #0
|
|
800044e: 6078 str r0, [r7, #4]
|
|
if(htim_pwm->Instance==TIM2)
|
|
8000450: 687b ldr r3, [r7, #4]
|
|
8000452: 681b ldr r3, [r3, #0]
|
|
8000454: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
8000458: d10b bne.n 8000472 <HAL_TIM_PWM_MspInit+0x2a>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM2_CLK_ENABLE();
|
|
800045a: 4b09 ldr r3, [pc, #36] ; (8000480 <HAL_TIM_PWM_MspInit+0x38>)
|
|
800045c: 69db ldr r3, [r3, #28]
|
|
800045e: 4a08 ldr r2, [pc, #32] ; (8000480 <HAL_TIM_PWM_MspInit+0x38>)
|
|
8000460: f043 0301 orr.w r3, r3, #1
|
|
8000464: 61d3 str r3, [r2, #28]
|
|
8000466: 4b06 ldr r3, [pc, #24] ; (8000480 <HAL_TIM_PWM_MspInit+0x38>)
|
|
8000468: 69db ldr r3, [r3, #28]
|
|
800046a: f003 0301 and.w r3, r3, #1
|
|
800046e: 60fb str r3, [r7, #12]
|
|
8000470: 68fb ldr r3, [r7, #12]
|
|
/* USER CODE BEGIN TIM2_MspInit 1 */
|
|
|
|
/* USER CODE END TIM2_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8000472: bf00 nop
|
|
8000474: 3714 adds r7, #20
|
|
8000476: 46bd mov sp, r7
|
|
8000478: f85d 7b04 ldr.w r7, [sp], #4
|
|
800047c: 4770 bx lr
|
|
800047e: bf00 nop
|
|
8000480: 40021000 .word 0x40021000
|
|
|
|
08000484 <HAL_TIM_MspPostInit>:
|
|
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
|
{
|
|
8000484: b580 push {r7, lr}
|
|
8000486: b088 sub sp, #32
|
|
8000488: af00 add r7, sp, #0
|
|
800048a: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800048c: f107 030c add.w r3, r7, #12
|
|
8000490: 2200 movs r2, #0
|
|
8000492: 601a str r2, [r3, #0]
|
|
8000494: 605a str r2, [r3, #4]
|
|
8000496: 609a str r2, [r3, #8]
|
|
8000498: 60da str r2, [r3, #12]
|
|
800049a: 611a str r2, [r3, #16]
|
|
if(htim->Instance==TIM2)
|
|
800049c: 687b ldr r3, [r7, #4]
|
|
800049e: 681b ldr r3, [r3, #0]
|
|
80004a0: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
80004a4: d11c bne.n 80004e0 <HAL_TIM_MspPostInit+0x5c>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 0 */
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80004a6: 4b10 ldr r3, [pc, #64] ; (80004e8 <HAL_TIM_MspPostInit+0x64>)
|
|
80004a8: 695b ldr r3, [r3, #20]
|
|
80004aa: 4a0f ldr r2, [pc, #60] ; (80004e8 <HAL_TIM_MspPostInit+0x64>)
|
|
80004ac: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
|
80004b0: 6153 str r3, [r2, #20]
|
|
80004b2: 4b0d ldr r3, [pc, #52] ; (80004e8 <HAL_TIM_MspPostInit+0x64>)
|
|
80004b4: 695b ldr r3, [r3, #20]
|
|
80004b6: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
80004ba: 60bb str r3, [r7, #8]
|
|
80004bc: 68bb ldr r3, [r7, #8]
|
|
/**TIM2 GPIO Configuration
|
|
PA1 ------> TIM2_CH2
|
|
*/
|
|
GPIO_InitStruct.Pin = PWM1_Out_Pin;
|
|
80004be: 2302 movs r3, #2
|
|
80004c0: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80004c2: 2302 movs r3, #2
|
|
80004c4: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80004c6: 2300 movs r3, #0
|
|
80004c8: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80004ca: 2300 movs r3, #0
|
|
80004cc: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
|
|
80004ce: 2301 movs r3, #1
|
|
80004d0: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(PWM1_Out_GPIO_Port, &GPIO_InitStruct);
|
|
80004d2: f107 030c add.w r3, r7, #12
|
|
80004d6: 4619 mov r1, r3
|
|
80004d8: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
80004dc: f000 f9dc bl 8000898 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM2_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
80004e0: bf00 nop
|
|
80004e2: 3720 adds r7, #32
|
|
80004e4: 46bd mov sp, r7
|
|
80004e6: bd80 pop {r7, pc}
|
|
80004e8: 40021000 .word 0x40021000
|
|
|
|
080004ec <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
80004ec: b480 push {r7}
|
|
80004ee: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
80004f0: e7fe b.n 80004f0 <NMI_Handler+0x4>
|
|
|
|
080004f2 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
80004f2: b480 push {r7}
|
|
80004f4: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
80004f6: e7fe b.n 80004f6 <HardFault_Handler+0x4>
|
|
|
|
080004f8 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
80004f8: b480 push {r7}
|
|
80004fa: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
80004fc: e7fe b.n 80004fc <MemManage_Handler+0x4>
|
|
|
|
080004fe <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pre-fetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
80004fe: b480 push {r7}
|
|
8000500: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8000502: e7fe b.n 8000502 <BusFault_Handler+0x4>
|
|
|
|
08000504 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8000504: b480 push {r7}
|
|
8000506: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8000508: e7fe b.n 8000508 <UsageFault_Handler+0x4>
|
|
|
|
0800050a <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
800050a: b480 push {r7}
|
|
800050c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
800050e: bf00 nop
|
|
8000510: 46bd mov sp, r7
|
|
8000512: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000516: 4770 bx lr
|
|
|
|
08000518 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8000518: b480 push {r7}
|
|
800051a: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
800051c: bf00 nop
|
|
800051e: 46bd mov sp, r7
|
|
8000520: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000524: 4770 bx lr
|
|
|
|
08000526 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8000526: b480 push {r7}
|
|
8000528: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
800052a: bf00 nop
|
|
800052c: 46bd mov sp, r7
|
|
800052e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000532: 4770 bx lr
|
|
|
|
08000534 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
8000534: b580 push {r7, lr}
|
|
8000536: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
8000538: f000 f884 bl 8000644 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
800053c: bf00 nop
|
|
800053e: bd80 pop {r7, pc}
|
|
|
|
08000540 <SystemInit>:
|
|
* @brief Setup the microcontroller system
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
8000540: b480 push {r7}
|
|
8000542: af00 add r7, sp, #0
|
|
/* FPU settings --------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
|
8000544: 4b06 ldr r3, [pc, #24] ; (8000560 <SystemInit+0x20>)
|
|
8000546: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800054a: 4a05 ldr r2, [pc, #20] ; (8000560 <SystemInit+0x20>)
|
|
800054c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
|
|
8000550: f8c2 3088 str.w r3, [r2, #136] ; 0x88
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
8000554: bf00 nop
|
|
8000556: 46bd mov sp, r7
|
|
8000558: f85d 7b04 ldr.w r7, [sp], #4
|
|
800055c: 4770 bx lr
|
|
800055e: bf00 nop
|
|
8000560: e000ed00 .word 0xe000ed00
|
|
|
|
08000564 <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* Atollic update: set stack pointer */
|
|
8000564: f8df d034 ldr.w sp, [pc, #52] ; 800059c <LoopForever+0x2>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8000568: f7ff ffea bl 8000540 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
800056c: 480c ldr r0, [pc, #48] ; (80005a0 <LoopForever+0x6>)
|
|
ldr r1, =_edata
|
|
800056e: 490d ldr r1, [pc, #52] ; (80005a4 <LoopForever+0xa>)
|
|
ldr r2, =_sidata
|
|
8000570: 4a0d ldr r2, [pc, #52] ; (80005a8 <LoopForever+0xe>)
|
|
movs r3, #0
|
|
8000572: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
8000574: e002 b.n 800057c <LoopCopyDataInit>
|
|
|
|
08000576 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
8000576: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8000578: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
800057a: 3304 adds r3, #4
|
|
|
|
0800057c <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
800057c: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
800057e: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8000580: d3f9 bcc.n 8000576 <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
8000582: 4a0a ldr r2, [pc, #40] ; (80005ac <LoopForever+0x12>)
|
|
ldr r4, =_ebss
|
|
8000584: 4c0a ldr r4, [pc, #40] ; (80005b0 <LoopForever+0x16>)
|
|
movs r3, #0
|
|
8000586: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8000588: e001 b.n 800058e <LoopFillZerobss>
|
|
|
|
0800058a <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
800058a: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
800058c: 3204 adds r2, #4
|
|
|
|
0800058e <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
800058e: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8000590: d3fb bcc.n 800058a <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8000592: f002 fb2f bl 8002bf4 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
8000596: f7ff fe17 bl 80001c8 <main>
|
|
|
|
0800059a <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
800059a: e7fe b.n 800059a <LoopForever>
|
|
ldr sp, =_estack /* Atollic update: set stack pointer */
|
|
800059c: 20004000 .word 0x20004000
|
|
ldr r0, =_sdata
|
|
80005a0: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
80005a4: 2000000c .word 0x2000000c
|
|
ldr r2, =_sidata
|
|
80005a8: 08002c9c .word 0x08002c9c
|
|
ldr r2, =_sbss
|
|
80005ac: 2000000c .word 0x2000000c
|
|
ldr r4, =_ebss
|
|
80005b0: 20000078 .word 0x20000078
|
|
|
|
080005b4 <ADC1_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
80005b4: e7fe b.n 80005b4 <ADC1_IRQHandler>
|
|
...
|
|
|
|
080005b8 <HAL_Init>:
|
|
* In the default implementation,Systick is used as source of time base.
|
|
* The tick variable is incremented each 1ms in its ISR.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
80005b8: b580 push {r7, lr}
|
|
80005ba: af00 add r7, sp, #0
|
|
/* Configure Flash prefetch */
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
80005bc: 4b08 ldr r3, [pc, #32] ; (80005e0 <HAL_Init+0x28>)
|
|
80005be: 681b ldr r3, [r3, #0]
|
|
80005c0: 4a07 ldr r2, [pc, #28] ; (80005e0 <HAL_Init+0x28>)
|
|
80005c2: f043 0310 orr.w r3, r3, #16
|
|
80005c6: 6013 str r3, [r2, #0]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
80005c8: 2003 movs r0, #3
|
|
80005ca: f000 f931 bl 8000830 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
80005ce: 200f movs r0, #15
|
|
80005d0: f000 f808 bl 80005e4 <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
80005d4: f7ff ff14 bl 8000400 <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80005d8: 2300 movs r3, #0
|
|
}
|
|
80005da: 4618 mov r0, r3
|
|
80005dc: bd80 pop {r7, pc}
|
|
80005de: bf00 nop
|
|
80005e0: 40022000 .word 0x40022000
|
|
|
|
080005e4 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
80005e4: b580 push {r7, lr}
|
|
80005e6: b082 sub sp, #8
|
|
80005e8: af00 add r7, sp, #0
|
|
80005ea: 6078 str r0, [r7, #4]
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
80005ec: 4b12 ldr r3, [pc, #72] ; (8000638 <HAL_InitTick+0x54>)
|
|
80005ee: 681a ldr r2, [r3, #0]
|
|
80005f0: 4b12 ldr r3, [pc, #72] ; (800063c <HAL_InitTick+0x58>)
|
|
80005f2: 781b ldrb r3, [r3, #0]
|
|
80005f4: 4619 mov r1, r3
|
|
80005f6: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
80005fa: fbb3 f3f1 udiv r3, r3, r1
|
|
80005fe: fbb2 f3f3 udiv r3, r2, r3
|
|
8000602: 4618 mov r0, r3
|
|
8000604: f000 f93b bl 800087e <HAL_SYSTICK_Config>
|
|
8000608: 4603 mov r3, r0
|
|
800060a: 2b00 cmp r3, #0
|
|
800060c: d001 beq.n 8000612 <HAL_InitTick+0x2e>
|
|
{
|
|
return HAL_ERROR;
|
|
800060e: 2301 movs r3, #1
|
|
8000610: e00e b.n 8000630 <HAL_InitTick+0x4c>
|
|
}
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8000612: 687b ldr r3, [r7, #4]
|
|
8000614: 2b0f cmp r3, #15
|
|
8000616: d80a bhi.n 800062e <HAL_InitTick+0x4a>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
8000618: 2200 movs r2, #0
|
|
800061a: 6879 ldr r1, [r7, #4]
|
|
800061c: f04f 30ff mov.w r0, #4294967295
|
|
8000620: f000 f911 bl 8000846 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8000624: 4a06 ldr r2, [pc, #24] ; (8000640 <HAL_InitTick+0x5c>)
|
|
8000626: 687b ldr r3, [r7, #4]
|
|
8000628: 6013 str r3, [r2, #0]
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
800062a: 2300 movs r3, #0
|
|
800062c: e000 b.n 8000630 <HAL_InitTick+0x4c>
|
|
return HAL_ERROR;
|
|
800062e: 2301 movs r3, #1
|
|
}
|
|
8000630: 4618 mov r0, r3
|
|
8000632: 3708 adds r7, #8
|
|
8000634: 46bd mov sp, r7
|
|
8000636: bd80 pop {r7, pc}
|
|
8000638: 20000000 .word 0x20000000
|
|
800063c: 20000008 .word 0x20000008
|
|
8000640: 20000004 .word 0x20000004
|
|
|
|
08000644 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8000644: b480 push {r7}
|
|
8000646: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
8000648: 4b06 ldr r3, [pc, #24] ; (8000664 <HAL_IncTick+0x20>)
|
|
800064a: 781b ldrb r3, [r3, #0]
|
|
800064c: 461a mov r2, r3
|
|
800064e: 4b06 ldr r3, [pc, #24] ; (8000668 <HAL_IncTick+0x24>)
|
|
8000650: 681b ldr r3, [r3, #0]
|
|
8000652: 4413 add r3, r2
|
|
8000654: 4a04 ldr r2, [pc, #16] ; (8000668 <HAL_IncTick+0x24>)
|
|
8000656: 6013 str r3, [r2, #0]
|
|
}
|
|
8000658: bf00 nop
|
|
800065a: 46bd mov sp, r7
|
|
800065c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000660: 4770 bx lr
|
|
8000662: bf00 nop
|
|
8000664: 20000008 .word 0x20000008
|
|
8000668: 20000074 .word 0x20000074
|
|
|
|
0800066c <HAL_GetTick>:
|
|
* @note The function is declared as __Weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
800066c: b480 push {r7}
|
|
800066e: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8000670: 4b03 ldr r3, [pc, #12] ; (8000680 <HAL_GetTick+0x14>)
|
|
8000672: 681b ldr r3, [r3, #0]
|
|
}
|
|
8000674: 4618 mov r0, r3
|
|
8000676: 46bd mov sp, r7
|
|
8000678: f85d 7b04 ldr.w r7, [sp], #4
|
|
800067c: 4770 bx lr
|
|
800067e: bf00 nop
|
|
8000680: 20000074 .word 0x20000074
|
|
|
|
08000684 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
8000684: b580 push {r7, lr}
|
|
8000686: b084 sub sp, #16
|
|
8000688: af00 add r7, sp, #0
|
|
800068a: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
800068c: f7ff ffee bl 800066c <HAL_GetTick>
|
|
8000690: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8000692: 687b ldr r3, [r7, #4]
|
|
8000694: 60fb str r3, [r7, #12]
|
|
|
|
/* Add freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
8000696: 68fb ldr r3, [r7, #12]
|
|
8000698: f1b3 3fff cmp.w r3, #4294967295
|
|
800069c: d005 beq.n 80006aa <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
800069e: 4b0a ldr r3, [pc, #40] ; (80006c8 <HAL_Delay+0x44>)
|
|
80006a0: 781b ldrb r3, [r3, #0]
|
|
80006a2: 461a mov r2, r3
|
|
80006a4: 68fb ldr r3, [r7, #12]
|
|
80006a6: 4413 add r3, r2
|
|
80006a8: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while((HAL_GetTick() - tickstart) < wait)
|
|
80006aa: bf00 nop
|
|
80006ac: f7ff ffde bl 800066c <HAL_GetTick>
|
|
80006b0: 4602 mov r2, r0
|
|
80006b2: 68bb ldr r3, [r7, #8]
|
|
80006b4: 1ad3 subs r3, r2, r3
|
|
80006b6: 68fa ldr r2, [r7, #12]
|
|
80006b8: 429a cmp r2, r3
|
|
80006ba: d8f7 bhi.n 80006ac <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
80006bc: bf00 nop
|
|
80006be: bf00 nop
|
|
80006c0: 3710 adds r7, #16
|
|
80006c2: 46bd mov sp, r7
|
|
80006c4: bd80 pop {r7, pc}
|
|
80006c6: bf00 nop
|
|
80006c8: 20000008 .word 0x20000008
|
|
|
|
080006cc <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
80006cc: b480 push {r7}
|
|
80006ce: b085 sub sp, #20
|
|
80006d0: af00 add r7, sp, #0
|
|
80006d2: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80006d4: 687b ldr r3, [r7, #4]
|
|
80006d6: f003 0307 and.w r3, r3, #7
|
|
80006da: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
80006dc: 4b0c ldr r3, [pc, #48] ; (8000710 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80006de: 68db ldr r3, [r3, #12]
|
|
80006e0: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
80006e2: 68ba ldr r2, [r7, #8]
|
|
80006e4: f64f 03ff movw r3, #63743 ; 0xf8ff
|
|
80006e8: 4013 ands r3, r2
|
|
80006ea: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
80006ec: 68fb ldr r3, [r7, #12]
|
|
80006ee: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80006f0: 68bb ldr r3, [r7, #8]
|
|
80006f2: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80006f4: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
|
|
80006f8: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
|
80006fc: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80006fe: 4a04 ldr r2, [pc, #16] ; (8000710 <__NVIC_SetPriorityGrouping+0x44>)
|
|
8000700: 68bb ldr r3, [r7, #8]
|
|
8000702: 60d3 str r3, [r2, #12]
|
|
}
|
|
8000704: bf00 nop
|
|
8000706: 3714 adds r7, #20
|
|
8000708: 46bd mov sp, r7
|
|
800070a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800070e: 4770 bx lr
|
|
8000710: e000ed00 .word 0xe000ed00
|
|
|
|
08000714 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8000714: b480 push {r7}
|
|
8000716: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8000718: 4b04 ldr r3, [pc, #16] ; (800072c <__NVIC_GetPriorityGrouping+0x18>)
|
|
800071a: 68db ldr r3, [r3, #12]
|
|
800071c: 0a1b lsrs r3, r3, #8
|
|
800071e: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8000722: 4618 mov r0, r3
|
|
8000724: 46bd mov sp, r7
|
|
8000726: f85d 7b04 ldr.w r7, [sp], #4
|
|
800072a: 4770 bx lr
|
|
800072c: e000ed00 .word 0xe000ed00
|
|
|
|
08000730 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8000730: b480 push {r7}
|
|
8000732: b083 sub sp, #12
|
|
8000734: af00 add r7, sp, #0
|
|
8000736: 4603 mov r3, r0
|
|
8000738: 6039 str r1, [r7, #0]
|
|
800073a: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
800073c: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8000740: 2b00 cmp r3, #0
|
|
8000742: db0a blt.n 800075a <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8000744: 683b ldr r3, [r7, #0]
|
|
8000746: b2da uxtb r2, r3
|
|
8000748: 490c ldr r1, [pc, #48] ; (800077c <__NVIC_SetPriority+0x4c>)
|
|
800074a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800074e: 0112 lsls r2, r2, #4
|
|
8000750: b2d2 uxtb r2, r2
|
|
8000752: 440b add r3, r1
|
|
8000754: f883 2300 strb.w r2, [r3, #768] ; 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8000758: e00a b.n 8000770 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
800075a: 683b ldr r3, [r7, #0]
|
|
800075c: b2da uxtb r2, r3
|
|
800075e: 4908 ldr r1, [pc, #32] ; (8000780 <__NVIC_SetPriority+0x50>)
|
|
8000760: 79fb ldrb r3, [r7, #7]
|
|
8000762: f003 030f and.w r3, r3, #15
|
|
8000766: 3b04 subs r3, #4
|
|
8000768: 0112 lsls r2, r2, #4
|
|
800076a: b2d2 uxtb r2, r2
|
|
800076c: 440b add r3, r1
|
|
800076e: 761a strb r2, [r3, #24]
|
|
}
|
|
8000770: bf00 nop
|
|
8000772: 370c adds r7, #12
|
|
8000774: 46bd mov sp, r7
|
|
8000776: f85d 7b04 ldr.w r7, [sp], #4
|
|
800077a: 4770 bx lr
|
|
800077c: e000e100 .word 0xe000e100
|
|
8000780: e000ed00 .word 0xe000ed00
|
|
|
|
08000784 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8000784: b480 push {r7}
|
|
8000786: b089 sub sp, #36 ; 0x24
|
|
8000788: af00 add r7, sp, #0
|
|
800078a: 60f8 str r0, [r7, #12]
|
|
800078c: 60b9 str r1, [r7, #8]
|
|
800078e: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8000790: 68fb ldr r3, [r7, #12]
|
|
8000792: f003 0307 and.w r3, r3, #7
|
|
8000796: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8000798: 69fb ldr r3, [r7, #28]
|
|
800079a: f1c3 0307 rsb r3, r3, #7
|
|
800079e: 2b04 cmp r3, #4
|
|
80007a0: bf28 it cs
|
|
80007a2: 2304 movcs r3, #4
|
|
80007a4: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
80007a6: 69fb ldr r3, [r7, #28]
|
|
80007a8: 3304 adds r3, #4
|
|
80007aa: 2b06 cmp r3, #6
|
|
80007ac: d902 bls.n 80007b4 <NVIC_EncodePriority+0x30>
|
|
80007ae: 69fb ldr r3, [r7, #28]
|
|
80007b0: 3b03 subs r3, #3
|
|
80007b2: e000 b.n 80007b6 <NVIC_EncodePriority+0x32>
|
|
80007b4: 2300 movs r3, #0
|
|
80007b6: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80007b8: f04f 32ff mov.w r2, #4294967295
|
|
80007bc: 69bb ldr r3, [r7, #24]
|
|
80007be: fa02 f303 lsl.w r3, r2, r3
|
|
80007c2: 43da mvns r2, r3
|
|
80007c4: 68bb ldr r3, [r7, #8]
|
|
80007c6: 401a ands r2, r3
|
|
80007c8: 697b ldr r3, [r7, #20]
|
|
80007ca: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
80007cc: f04f 31ff mov.w r1, #4294967295
|
|
80007d0: 697b ldr r3, [r7, #20]
|
|
80007d2: fa01 f303 lsl.w r3, r1, r3
|
|
80007d6: 43d9 mvns r1, r3
|
|
80007d8: 687b ldr r3, [r7, #4]
|
|
80007da: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80007dc: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
80007de: 4618 mov r0, r3
|
|
80007e0: 3724 adds r7, #36 ; 0x24
|
|
80007e2: 46bd mov sp, r7
|
|
80007e4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80007e8: 4770 bx lr
|
|
...
|
|
|
|
080007ec <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
80007ec: b580 push {r7, lr}
|
|
80007ee: b082 sub sp, #8
|
|
80007f0: af00 add r7, sp, #0
|
|
80007f2: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
80007f4: 687b ldr r3, [r7, #4]
|
|
80007f6: 3b01 subs r3, #1
|
|
80007f8: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
|
|
80007fc: d301 bcc.n 8000802 <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
80007fe: 2301 movs r3, #1
|
|
8000800: e00f b.n 8000822 <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8000802: 4a0a ldr r2, [pc, #40] ; (800082c <SysTick_Config+0x40>)
|
|
8000804: 687b ldr r3, [r7, #4]
|
|
8000806: 3b01 subs r3, #1
|
|
8000808: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
800080a: 210f movs r1, #15
|
|
800080c: f04f 30ff mov.w r0, #4294967295
|
|
8000810: f7ff ff8e bl 8000730 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8000814: 4b05 ldr r3, [pc, #20] ; (800082c <SysTick_Config+0x40>)
|
|
8000816: 2200 movs r2, #0
|
|
8000818: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
800081a: 4b04 ldr r3, [pc, #16] ; (800082c <SysTick_Config+0x40>)
|
|
800081c: 2207 movs r2, #7
|
|
800081e: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8000820: 2300 movs r3, #0
|
|
}
|
|
8000822: 4618 mov r0, r3
|
|
8000824: 3708 adds r7, #8
|
|
8000826: 46bd mov sp, r7
|
|
8000828: bd80 pop {r7, pc}
|
|
800082a: bf00 nop
|
|
800082c: e000e010 .word 0xe000e010
|
|
|
|
08000830 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8000830: b580 push {r7, lr}
|
|
8000832: b082 sub sp, #8
|
|
8000834: af00 add r7, sp, #0
|
|
8000836: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8000838: 6878 ldr r0, [r7, #4]
|
|
800083a: f7ff ff47 bl 80006cc <__NVIC_SetPriorityGrouping>
|
|
}
|
|
800083e: bf00 nop
|
|
8000840: 3708 adds r7, #8
|
|
8000842: 46bd mov sp, r7
|
|
8000844: bd80 pop {r7, pc}
|
|
|
|
08000846 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8000846: b580 push {r7, lr}
|
|
8000848: b086 sub sp, #24
|
|
800084a: af00 add r7, sp, #0
|
|
800084c: 4603 mov r3, r0
|
|
800084e: 60b9 str r1, [r7, #8]
|
|
8000850: 607a str r2, [r7, #4]
|
|
8000852: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
8000854: 2300 movs r3, #0
|
|
8000856: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8000858: f7ff ff5c bl 8000714 <__NVIC_GetPriorityGrouping>
|
|
800085c: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
800085e: 687a ldr r2, [r7, #4]
|
|
8000860: 68b9 ldr r1, [r7, #8]
|
|
8000862: 6978 ldr r0, [r7, #20]
|
|
8000864: f7ff ff8e bl 8000784 <NVIC_EncodePriority>
|
|
8000868: 4602 mov r2, r0
|
|
800086a: f997 300f ldrsb.w r3, [r7, #15]
|
|
800086e: 4611 mov r1, r2
|
|
8000870: 4618 mov r0, r3
|
|
8000872: f7ff ff5d bl 8000730 <__NVIC_SetPriority>
|
|
}
|
|
8000876: bf00 nop
|
|
8000878: 3718 adds r7, #24
|
|
800087a: 46bd mov sp, r7
|
|
800087c: bd80 pop {r7, pc}
|
|
|
|
0800087e <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
800087e: b580 push {r7, lr}
|
|
8000880: b082 sub sp, #8
|
|
8000882: af00 add r7, sp, #0
|
|
8000884: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8000886: 6878 ldr r0, [r7, #4]
|
|
8000888: f7ff ffb0 bl 80007ec <SysTick_Config>
|
|
800088c: 4603 mov r3, r0
|
|
}
|
|
800088e: 4618 mov r0, r3
|
|
8000890: 3708 adds r7, #8
|
|
8000892: 46bd mov sp, r7
|
|
8000894: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08000898 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8000898: b480 push {r7}
|
|
800089a: b087 sub sp, #28
|
|
800089c: af00 add r7, sp, #0
|
|
800089e: 6078 str r0, [r7, #4]
|
|
80008a0: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
80008a2: 2300 movs r3, #0
|
|
80008a4: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
80008a6: e14e b.n 8000b46 <HAL_GPIO_Init+0x2ae>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
|
80008a8: 683b ldr r3, [r7, #0]
|
|
80008aa: 681a ldr r2, [r3, #0]
|
|
80008ac: 2101 movs r1, #1
|
|
80008ae: 697b ldr r3, [r7, #20]
|
|
80008b0: fa01 f303 lsl.w r3, r1, r3
|
|
80008b4: 4013 ands r3, r2
|
|
80008b6: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
80008b8: 68fb ldr r3, [r7, #12]
|
|
80008ba: 2b00 cmp r3, #0
|
|
80008bc: f000 8140 beq.w 8000b40 <HAL_GPIO_Init+0x2a8>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
80008c0: 683b ldr r3, [r7, #0]
|
|
80008c2: 685b ldr r3, [r3, #4]
|
|
80008c4: f003 0303 and.w r3, r3, #3
|
|
80008c8: 2b01 cmp r3, #1
|
|
80008ca: d005 beq.n 80008d8 <HAL_GPIO_Init+0x40>
|
|
80008cc: 683b ldr r3, [r7, #0]
|
|
80008ce: 685b ldr r3, [r3, #4]
|
|
80008d0: f003 0303 and.w r3, r3, #3
|
|
80008d4: 2b02 cmp r3, #2
|
|
80008d6: d130 bne.n 800093a <HAL_GPIO_Init+0xa2>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
80008d8: 687b ldr r3, [r7, #4]
|
|
80008da: 689b ldr r3, [r3, #8]
|
|
80008dc: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
|
|
80008de: 697b ldr r3, [r7, #20]
|
|
80008e0: 005b lsls r3, r3, #1
|
|
80008e2: 2203 movs r2, #3
|
|
80008e4: fa02 f303 lsl.w r3, r2, r3
|
|
80008e8: 43db mvns r3, r3
|
|
80008ea: 693a ldr r2, [r7, #16]
|
|
80008ec: 4013 ands r3, r2
|
|
80008ee: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
|
80008f0: 683b ldr r3, [r7, #0]
|
|
80008f2: 68da ldr r2, [r3, #12]
|
|
80008f4: 697b ldr r3, [r7, #20]
|
|
80008f6: 005b lsls r3, r3, #1
|
|
80008f8: fa02 f303 lsl.w r3, r2, r3
|
|
80008fc: 693a ldr r2, [r7, #16]
|
|
80008fe: 4313 orrs r3, r2
|
|
8000900: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
8000902: 687b ldr r3, [r7, #4]
|
|
8000904: 693a ldr r2, [r7, #16]
|
|
8000906: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
8000908: 687b ldr r3, [r7, #4]
|
|
800090a: 685b ldr r3, [r3, #4]
|
|
800090c: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
800090e: 2201 movs r2, #1
|
|
8000910: 697b ldr r3, [r7, #20]
|
|
8000912: fa02 f303 lsl.w r3, r2, r3
|
|
8000916: 43db mvns r3, r3
|
|
8000918: 693a ldr r2, [r7, #16]
|
|
800091a: 4013 ands r3, r2
|
|
800091c: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
800091e: 683b ldr r3, [r7, #0]
|
|
8000920: 685b ldr r3, [r3, #4]
|
|
8000922: 091b lsrs r3, r3, #4
|
|
8000924: f003 0201 and.w r2, r3, #1
|
|
8000928: 697b ldr r3, [r7, #20]
|
|
800092a: fa02 f303 lsl.w r3, r2, r3
|
|
800092e: 693a ldr r2, [r7, #16]
|
|
8000930: 4313 orrs r3, r2
|
|
8000932: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
8000934: 687b ldr r3, [r7, #4]
|
|
8000936: 693a ldr r2, [r7, #16]
|
|
8000938: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
800093a: 683b ldr r3, [r7, #0]
|
|
800093c: 685b ldr r3, [r3, #4]
|
|
800093e: f003 0303 and.w r3, r3, #3
|
|
8000942: 2b03 cmp r3, #3
|
|
8000944: d017 beq.n 8000976 <HAL_GPIO_Init+0xde>
|
|
{
|
|
/* Check the Pull parameter */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
8000946: 687b ldr r3, [r7, #4]
|
|
8000948: 68db ldr r3, [r3, #12]
|
|
800094a: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
|
|
800094c: 697b ldr r3, [r7, #20]
|
|
800094e: 005b lsls r3, r3, #1
|
|
8000950: 2203 movs r2, #3
|
|
8000952: fa02 f303 lsl.w r3, r2, r3
|
|
8000956: 43db mvns r3, r3
|
|
8000958: 693a ldr r2, [r7, #16]
|
|
800095a: 4013 ands r3, r2
|
|
800095c: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2u));
|
|
800095e: 683b ldr r3, [r7, #0]
|
|
8000960: 689a ldr r2, [r3, #8]
|
|
8000962: 697b ldr r3, [r7, #20]
|
|
8000964: 005b lsls r3, r3, #1
|
|
8000966: fa02 f303 lsl.w r3, r2, r3
|
|
800096a: 693a ldr r2, [r7, #16]
|
|
800096c: 4313 orrs r3, r2
|
|
800096e: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
8000970: 687b ldr r3, [r7, #4]
|
|
8000972: 693a ldr r2, [r7, #16]
|
|
8000974: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Alternate function mode selection */
|
|
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8000976: 683b ldr r3, [r7, #0]
|
|
8000978: 685b ldr r3, [r3, #4]
|
|
800097a: f003 0303 and.w r3, r3, #3
|
|
800097e: 2b02 cmp r3, #2
|
|
8000980: d123 bne.n 80009ca <HAL_GPIO_Init+0x132>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3u];
|
|
8000982: 697b ldr r3, [r7, #20]
|
|
8000984: 08da lsrs r2, r3, #3
|
|
8000986: 687b ldr r3, [r7, #4]
|
|
8000988: 3208 adds r2, #8
|
|
800098a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800098e: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
|
8000990: 697b ldr r3, [r7, #20]
|
|
8000992: f003 0307 and.w r3, r3, #7
|
|
8000996: 009b lsls r3, r3, #2
|
|
8000998: 220f movs r2, #15
|
|
800099a: fa02 f303 lsl.w r3, r2, r3
|
|
800099e: 43db mvns r3, r3
|
|
80009a0: 693a ldr r2, [r7, #16]
|
|
80009a2: 4013 ands r3, r2
|
|
80009a4: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
|
80009a6: 683b ldr r3, [r7, #0]
|
|
80009a8: 691a ldr r2, [r3, #16]
|
|
80009aa: 697b ldr r3, [r7, #20]
|
|
80009ac: f003 0307 and.w r3, r3, #7
|
|
80009b0: 009b lsls r3, r3, #2
|
|
80009b2: fa02 f303 lsl.w r3, r2, r3
|
|
80009b6: 693a ldr r2, [r7, #16]
|
|
80009b8: 4313 orrs r3, r2
|
|
80009ba: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3u] = temp;
|
|
80009bc: 697b ldr r3, [r7, #20]
|
|
80009be: 08da lsrs r2, r3, #3
|
|
80009c0: 687b ldr r3, [r7, #4]
|
|
80009c2: 3208 adds r2, #8
|
|
80009c4: 6939 ldr r1, [r7, #16]
|
|
80009c6: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
80009ca: 687b ldr r3, [r7, #4]
|
|
80009cc: 681b ldr r3, [r3, #0]
|
|
80009ce: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
|
|
80009d0: 697b ldr r3, [r7, #20]
|
|
80009d2: 005b lsls r3, r3, #1
|
|
80009d4: 2203 movs r2, #3
|
|
80009d6: fa02 f303 lsl.w r3, r2, r3
|
|
80009da: 43db mvns r3, r3
|
|
80009dc: 693a ldr r2, [r7, #16]
|
|
80009de: 4013 ands r3, r2
|
|
80009e0: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
|
80009e2: 683b ldr r3, [r7, #0]
|
|
80009e4: 685b ldr r3, [r3, #4]
|
|
80009e6: f003 0203 and.w r2, r3, #3
|
|
80009ea: 697b ldr r3, [r7, #20]
|
|
80009ec: 005b lsls r3, r3, #1
|
|
80009ee: fa02 f303 lsl.w r3, r2, r3
|
|
80009f2: 693a ldr r2, [r7, #16]
|
|
80009f4: 4313 orrs r3, r2
|
|
80009f6: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
80009f8: 687b ldr r3, [r7, #4]
|
|
80009fa: 693a ldr r2, [r7, #16]
|
|
80009fc: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
|
80009fe: 683b ldr r3, [r7, #0]
|
|
8000a00: 685b ldr r3, [r3, #4]
|
|
8000a02: f403 3340 and.w r3, r3, #196608 ; 0x30000
|
|
8000a06: 2b00 cmp r3, #0
|
|
8000a08: f000 809a beq.w 8000b40 <HAL_GPIO_Init+0x2a8>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8000a0c: 4b55 ldr r3, [pc, #340] ; (8000b64 <HAL_GPIO_Init+0x2cc>)
|
|
8000a0e: 699b ldr r3, [r3, #24]
|
|
8000a10: 4a54 ldr r2, [pc, #336] ; (8000b64 <HAL_GPIO_Init+0x2cc>)
|
|
8000a12: f043 0301 orr.w r3, r3, #1
|
|
8000a16: 6193 str r3, [r2, #24]
|
|
8000a18: 4b52 ldr r3, [pc, #328] ; (8000b64 <HAL_GPIO_Init+0x2cc>)
|
|
8000a1a: 699b ldr r3, [r3, #24]
|
|
8000a1c: f003 0301 and.w r3, r3, #1
|
|
8000a20: 60bb str r3, [r7, #8]
|
|
8000a22: 68bb ldr r3, [r7, #8]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2u];
|
|
8000a24: 4a50 ldr r2, [pc, #320] ; (8000b68 <HAL_GPIO_Init+0x2d0>)
|
|
8000a26: 697b ldr r3, [r7, #20]
|
|
8000a28: 089b lsrs r3, r3, #2
|
|
8000a2a: 3302 adds r3, #2
|
|
8000a2c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8000a30: 613b str r3, [r7, #16]
|
|
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
|
8000a32: 697b ldr r3, [r7, #20]
|
|
8000a34: f003 0303 and.w r3, r3, #3
|
|
8000a38: 009b lsls r3, r3, #2
|
|
8000a3a: 220f movs r2, #15
|
|
8000a3c: fa02 f303 lsl.w r3, r2, r3
|
|
8000a40: 43db mvns r3, r3
|
|
8000a42: 693a ldr r2, [r7, #16]
|
|
8000a44: 4013 ands r3, r2
|
|
8000a46: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
|
8000a48: 687b ldr r3, [r7, #4]
|
|
8000a4a: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000
|
|
8000a4e: d013 beq.n 8000a78 <HAL_GPIO_Init+0x1e0>
|
|
8000a50: 687b ldr r3, [r7, #4]
|
|
8000a52: 4a46 ldr r2, [pc, #280] ; (8000b6c <HAL_GPIO_Init+0x2d4>)
|
|
8000a54: 4293 cmp r3, r2
|
|
8000a56: d00d beq.n 8000a74 <HAL_GPIO_Init+0x1dc>
|
|
8000a58: 687b ldr r3, [r7, #4]
|
|
8000a5a: 4a45 ldr r2, [pc, #276] ; (8000b70 <HAL_GPIO_Init+0x2d8>)
|
|
8000a5c: 4293 cmp r3, r2
|
|
8000a5e: d007 beq.n 8000a70 <HAL_GPIO_Init+0x1d8>
|
|
8000a60: 687b ldr r3, [r7, #4]
|
|
8000a62: 4a44 ldr r2, [pc, #272] ; (8000b74 <HAL_GPIO_Init+0x2dc>)
|
|
8000a64: 4293 cmp r3, r2
|
|
8000a66: d101 bne.n 8000a6c <HAL_GPIO_Init+0x1d4>
|
|
8000a68: 2303 movs r3, #3
|
|
8000a6a: e006 b.n 8000a7a <HAL_GPIO_Init+0x1e2>
|
|
8000a6c: 2305 movs r3, #5
|
|
8000a6e: e004 b.n 8000a7a <HAL_GPIO_Init+0x1e2>
|
|
8000a70: 2302 movs r3, #2
|
|
8000a72: e002 b.n 8000a7a <HAL_GPIO_Init+0x1e2>
|
|
8000a74: 2301 movs r3, #1
|
|
8000a76: e000 b.n 8000a7a <HAL_GPIO_Init+0x1e2>
|
|
8000a78: 2300 movs r3, #0
|
|
8000a7a: 697a ldr r2, [r7, #20]
|
|
8000a7c: f002 0203 and.w r2, r2, #3
|
|
8000a80: 0092 lsls r2, r2, #2
|
|
8000a82: 4093 lsls r3, r2
|
|
8000a84: 693a ldr r2, [r7, #16]
|
|
8000a86: 4313 orrs r3, r2
|
|
8000a88: 613b str r3, [r7, #16]
|
|
SYSCFG->EXTICR[position >> 2u] = temp;
|
|
8000a8a: 4937 ldr r1, [pc, #220] ; (8000b68 <HAL_GPIO_Init+0x2d0>)
|
|
8000a8c: 697b ldr r3, [r7, #20]
|
|
8000a8e: 089b lsrs r3, r3, #2
|
|
8000a90: 3302 adds r3, #2
|
|
8000a92: 693a ldr r2, [r7, #16]
|
|
8000a94: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR;
|
|
8000a98: 4b37 ldr r3, [pc, #220] ; (8000b78 <HAL_GPIO_Init+0x2e0>)
|
|
8000a9a: 689b ldr r3, [r3, #8]
|
|
8000a9c: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8000a9e: 68fb ldr r3, [r7, #12]
|
|
8000aa0: 43db mvns r3, r3
|
|
8000aa2: 693a ldr r2, [r7, #16]
|
|
8000aa4: 4013 ands r3, r2
|
|
8000aa6: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
|
8000aa8: 683b ldr r3, [r7, #0]
|
|
8000aaa: 685b ldr r3, [r3, #4]
|
|
8000aac: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
8000ab0: 2b00 cmp r3, #0
|
|
8000ab2: d003 beq.n 8000abc <HAL_GPIO_Init+0x224>
|
|
{
|
|
temp |= iocurrent;
|
|
8000ab4: 693a ldr r2, [r7, #16]
|
|
8000ab6: 68fb ldr r3, [r7, #12]
|
|
8000ab8: 4313 orrs r3, r2
|
|
8000aba: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR = temp;
|
|
8000abc: 4a2e ldr r2, [pc, #184] ; (8000b78 <HAL_GPIO_Init+0x2e0>)
|
|
8000abe: 693b ldr r3, [r7, #16]
|
|
8000ac0: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR;
|
|
8000ac2: 4b2d ldr r3, [pc, #180] ; (8000b78 <HAL_GPIO_Init+0x2e0>)
|
|
8000ac4: 68db ldr r3, [r3, #12]
|
|
8000ac6: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8000ac8: 68fb ldr r3, [r7, #12]
|
|
8000aca: 43db mvns r3, r3
|
|
8000acc: 693a ldr r2, [r7, #16]
|
|
8000ace: 4013 ands r3, r2
|
|
8000ad0: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
|
8000ad2: 683b ldr r3, [r7, #0]
|
|
8000ad4: 685b ldr r3, [r3, #4]
|
|
8000ad6: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
|
8000ada: 2b00 cmp r3, #0
|
|
8000adc: d003 beq.n 8000ae6 <HAL_GPIO_Init+0x24e>
|
|
{
|
|
temp |= iocurrent;
|
|
8000ade: 693a ldr r2, [r7, #16]
|
|
8000ae0: 68fb ldr r3, [r7, #12]
|
|
8000ae2: 4313 orrs r3, r2
|
|
8000ae4: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR = temp;
|
|
8000ae6: 4a24 ldr r2, [pc, #144] ; (8000b78 <HAL_GPIO_Init+0x2e0>)
|
|
8000ae8: 693b ldr r3, [r7, #16]
|
|
8000aea: 60d3 str r3, [r2, #12]
|
|
|
|
temp = EXTI->EMR;
|
|
8000aec: 4b22 ldr r3, [pc, #136] ; (8000b78 <HAL_GPIO_Init+0x2e0>)
|
|
8000aee: 685b ldr r3, [r3, #4]
|
|
8000af0: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8000af2: 68fb ldr r3, [r7, #12]
|
|
8000af4: 43db mvns r3, r3
|
|
8000af6: 693a ldr r2, [r7, #16]
|
|
8000af8: 4013 ands r3, r2
|
|
8000afa: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
|
8000afc: 683b ldr r3, [r7, #0]
|
|
8000afe: 685b ldr r3, [r3, #4]
|
|
8000b00: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8000b04: 2b00 cmp r3, #0
|
|
8000b06: d003 beq.n 8000b10 <HAL_GPIO_Init+0x278>
|
|
{
|
|
temp |= iocurrent;
|
|
8000b08: 693a ldr r2, [r7, #16]
|
|
8000b0a: 68fb ldr r3, [r7, #12]
|
|
8000b0c: 4313 orrs r3, r2
|
|
8000b0e: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR = temp;
|
|
8000b10: 4a19 ldr r2, [pc, #100] ; (8000b78 <HAL_GPIO_Init+0x2e0>)
|
|
8000b12: 693b ldr r3, [r7, #16]
|
|
8000b14: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR;
|
|
8000b16: 4b18 ldr r3, [pc, #96] ; (8000b78 <HAL_GPIO_Init+0x2e0>)
|
|
8000b18: 681b ldr r3, [r3, #0]
|
|
8000b1a: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8000b1c: 68fb ldr r3, [r7, #12]
|
|
8000b1e: 43db mvns r3, r3
|
|
8000b20: 693a ldr r2, [r7, #16]
|
|
8000b22: 4013 ands r3, r2
|
|
8000b24: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
|
8000b26: 683b ldr r3, [r7, #0]
|
|
8000b28: 685b ldr r3, [r3, #4]
|
|
8000b2a: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8000b2e: 2b00 cmp r3, #0
|
|
8000b30: d003 beq.n 8000b3a <HAL_GPIO_Init+0x2a2>
|
|
{
|
|
temp |= iocurrent;
|
|
8000b32: 693a ldr r2, [r7, #16]
|
|
8000b34: 68fb ldr r3, [r7, #12]
|
|
8000b36: 4313 orrs r3, r2
|
|
8000b38: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR = temp;
|
|
8000b3a: 4a0f ldr r2, [pc, #60] ; (8000b78 <HAL_GPIO_Init+0x2e0>)
|
|
8000b3c: 693b ldr r3, [r7, #16]
|
|
8000b3e: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8000b40: 697b ldr r3, [r7, #20]
|
|
8000b42: 3301 adds r3, #1
|
|
8000b44: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8000b46: 683b ldr r3, [r7, #0]
|
|
8000b48: 681a ldr r2, [r3, #0]
|
|
8000b4a: 697b ldr r3, [r7, #20]
|
|
8000b4c: fa22 f303 lsr.w r3, r2, r3
|
|
8000b50: 2b00 cmp r3, #0
|
|
8000b52: f47f aea9 bne.w 80008a8 <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
8000b56: bf00 nop
|
|
8000b58: bf00 nop
|
|
8000b5a: 371c adds r7, #28
|
|
8000b5c: 46bd mov sp, r7
|
|
8000b5e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000b62: 4770 bx lr
|
|
8000b64: 40021000 .word 0x40021000
|
|
8000b68: 40010000 .word 0x40010000
|
|
8000b6c: 48000400 .word 0x48000400
|
|
8000b70: 48000800 .word 0x48000800
|
|
8000b74: 48000c00 .word 0x48000c00
|
|
8000b78: 40010400 .word 0x40010400
|
|
|
|
08000b7c <HAL_GPIO_ReadPin>:
|
|
* @param GPIO_Pin specifies the port bit to read.
|
|
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
|
* @retval The input port pin value.
|
|
*/
|
|
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
8000b7c: b480 push {r7}
|
|
8000b7e: b085 sub sp, #20
|
|
8000b80: af00 add r7, sp, #0
|
|
8000b82: 6078 str r0, [r7, #4]
|
|
8000b84: 460b mov r3, r1
|
|
8000b86: 807b strh r3, [r7, #2]
|
|
GPIO_PinState bitstatus;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
|
8000b88: 687b ldr r3, [r7, #4]
|
|
8000b8a: 691a ldr r2, [r3, #16]
|
|
8000b8c: 887b ldrh r3, [r7, #2]
|
|
8000b8e: 4013 ands r3, r2
|
|
8000b90: 2b00 cmp r3, #0
|
|
8000b92: d002 beq.n 8000b9a <HAL_GPIO_ReadPin+0x1e>
|
|
{
|
|
bitstatus = GPIO_PIN_SET;
|
|
8000b94: 2301 movs r3, #1
|
|
8000b96: 73fb strb r3, [r7, #15]
|
|
8000b98: e001 b.n 8000b9e <HAL_GPIO_ReadPin+0x22>
|
|
}
|
|
else
|
|
{
|
|
bitstatus = GPIO_PIN_RESET;
|
|
8000b9a: 2300 movs r3, #0
|
|
8000b9c: 73fb strb r3, [r7, #15]
|
|
}
|
|
return bitstatus;
|
|
8000b9e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8000ba0: 4618 mov r0, r3
|
|
8000ba2: 3714 adds r7, #20
|
|
8000ba4: 46bd mov sp, r7
|
|
8000ba6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000baa: 4770 bx lr
|
|
|
|
08000bac <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8000bac: b480 push {r7}
|
|
8000bae: b083 sub sp, #12
|
|
8000bb0: af00 add r7, sp, #0
|
|
8000bb2: 6078 str r0, [r7, #4]
|
|
8000bb4: 460b mov r3, r1
|
|
8000bb6: 807b strh r3, [r7, #2]
|
|
8000bb8: 4613 mov r3, r2
|
|
8000bba: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
8000bbc: 787b ldrb r3, [r7, #1]
|
|
8000bbe: 2b00 cmp r3, #0
|
|
8000bc0: d003 beq.n 8000bca <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
8000bc2: 887a ldrh r2, [r7, #2]
|
|
8000bc4: 687b ldr r3, [r7, #4]
|
|
8000bc6: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
8000bc8: e002 b.n 8000bd0 <HAL_GPIO_WritePin+0x24>
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
8000bca: 887a ldrh r2, [r7, #2]
|
|
8000bcc: 687b ldr r3, [r7, #4]
|
|
8000bce: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
8000bd0: bf00 nop
|
|
8000bd2: 370c adds r7, #12
|
|
8000bd4: 46bd mov sp, r7
|
|
8000bd6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000bda: 4770 bx lr
|
|
|
|
08000bdc <HAL_RCC_OscConfig>:
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8000bdc: b580 push {r7, lr}
|
|
8000bde: f5ad 7d00 sub.w sp, sp, #512 ; 0x200
|
|
8000be2: af00 add r7, sp, #0
|
|
8000be4: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8000be8: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8000bec: 6018 str r0, [r3, #0]
|
|
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
|
|
uint32_t pll_config2;
|
|
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_OscInitStruct == NULL)
|
|
8000bee: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8000bf2: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8000bf6: 681b ldr r3, [r3, #0]
|
|
8000bf8: 2b00 cmp r3, #0
|
|
8000bfa: d102 bne.n 8000c02 <HAL_RCC_OscConfig+0x26>
|
|
{
|
|
return HAL_ERROR;
|
|
8000bfc: 2301 movs r3, #1
|
|
8000bfe: f001 b823 b.w 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8000c02: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8000c06: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8000c0a: 681b ldr r3, [r3, #0]
|
|
8000c0c: 681b ldr r3, [r3, #0]
|
|
8000c0e: f003 0301 and.w r3, r3, #1
|
|
8000c12: 2b00 cmp r3, #0
|
|
8000c14: f000 817d beq.w 8000f12 <HAL_RCC_OscConfig+0x336>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
8000c18: 4bbc ldr r3, [pc, #752] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000c1a: 685b ldr r3, [r3, #4]
|
|
8000c1c: f003 030c and.w r3, r3, #12
|
|
8000c20: 2b04 cmp r3, #4
|
|
8000c22: d00c beq.n 8000c3e <HAL_RCC_OscConfig+0x62>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
|
|
8000c24: 4bb9 ldr r3, [pc, #740] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000c26: 685b ldr r3, [r3, #4]
|
|
8000c28: f003 030c and.w r3, r3, #12
|
|
8000c2c: 2b08 cmp r3, #8
|
|
8000c2e: d15c bne.n 8000cea <HAL_RCC_OscConfig+0x10e>
|
|
8000c30: 4bb6 ldr r3, [pc, #728] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000c32: 685b ldr r3, [r3, #4]
|
|
8000c34: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8000c38: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8000c3c: d155 bne.n 8000cea <HAL_RCC_OscConfig+0x10e>
|
|
8000c3e: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8000c42: f8c7 31f0 str.w r3, [r7, #496] ; 0x1f0
|
|
uint32_t result;
|
|
|
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
|
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
|
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8000c46: f8d7 31f0 ldr.w r3, [r7, #496] ; 0x1f0
|
|
8000c4a: fa93 f3a3 rbit r3, r3
|
|
8000c4e: f8c7 31ec str.w r3, [r7, #492] ; 0x1ec
|
|
result |= value & 1U;
|
|
s--;
|
|
}
|
|
result <<= s; /* shift when v's highest bits are zero */
|
|
#endif
|
|
return result;
|
|
8000c52: f8d7 31ec ldr.w r3, [r7, #492] ; 0x1ec
|
|
{
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8000c56: fab3 f383 clz r3, r3
|
|
8000c5a: b2db uxtb r3, r3
|
|
8000c5c: 095b lsrs r3, r3, #5
|
|
8000c5e: b2db uxtb r3, r3
|
|
8000c60: f043 0301 orr.w r3, r3, #1
|
|
8000c64: b2db uxtb r3, r3
|
|
8000c66: 2b01 cmp r3, #1
|
|
8000c68: d102 bne.n 8000c70 <HAL_RCC_OscConfig+0x94>
|
|
8000c6a: 4ba8 ldr r3, [pc, #672] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000c6c: 681b ldr r3, [r3, #0]
|
|
8000c6e: e015 b.n 8000c9c <HAL_RCC_OscConfig+0xc0>
|
|
8000c70: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8000c74: f8c7 31e8 str.w r3, [r7, #488] ; 0x1e8
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8000c78: f8d7 31e8 ldr.w r3, [r7, #488] ; 0x1e8
|
|
8000c7c: fa93 f3a3 rbit r3, r3
|
|
8000c80: f8c7 31e4 str.w r3, [r7, #484] ; 0x1e4
|
|
8000c84: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8000c88: f8c7 31e0 str.w r3, [r7, #480] ; 0x1e0
|
|
8000c8c: f8d7 31e0 ldr.w r3, [r7, #480] ; 0x1e0
|
|
8000c90: fa93 f3a3 rbit r3, r3
|
|
8000c94: f8c7 31dc str.w r3, [r7, #476] ; 0x1dc
|
|
8000c98: 4b9c ldr r3, [pc, #624] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000c9a: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8000c9c: f44f 3200 mov.w r2, #131072 ; 0x20000
|
|
8000ca0: f8c7 21d8 str.w r2, [r7, #472] ; 0x1d8
|
|
8000ca4: f8d7 21d8 ldr.w r2, [r7, #472] ; 0x1d8
|
|
8000ca8: fa92 f2a2 rbit r2, r2
|
|
8000cac: f8c7 21d4 str.w r2, [r7, #468] ; 0x1d4
|
|
return result;
|
|
8000cb0: f8d7 21d4 ldr.w r2, [r7, #468] ; 0x1d4
|
|
8000cb4: fab2 f282 clz r2, r2
|
|
8000cb8: b2d2 uxtb r2, r2
|
|
8000cba: f042 0220 orr.w r2, r2, #32
|
|
8000cbe: b2d2 uxtb r2, r2
|
|
8000cc0: f002 021f and.w r2, r2, #31
|
|
8000cc4: 2101 movs r1, #1
|
|
8000cc6: fa01 f202 lsl.w r2, r1, r2
|
|
8000cca: 4013 ands r3, r2
|
|
8000ccc: 2b00 cmp r3, #0
|
|
8000cce: f000 811f beq.w 8000f10 <HAL_RCC_OscConfig+0x334>
|
|
8000cd2: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8000cd6: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8000cda: 681b ldr r3, [r3, #0]
|
|
8000cdc: 685b ldr r3, [r3, #4]
|
|
8000cde: 2b00 cmp r3, #0
|
|
8000ce0: f040 8116 bne.w 8000f10 <HAL_RCC_OscConfig+0x334>
|
|
{
|
|
return HAL_ERROR;
|
|
8000ce4: 2301 movs r3, #1
|
|
8000ce6: f000 bfaf b.w 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8000cea: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8000cee: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8000cf2: 681b ldr r3, [r3, #0]
|
|
8000cf4: 685b ldr r3, [r3, #4]
|
|
8000cf6: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8000cfa: d106 bne.n 8000d0a <HAL_RCC_OscConfig+0x12e>
|
|
8000cfc: 4b83 ldr r3, [pc, #524] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000cfe: 681b ldr r3, [r3, #0]
|
|
8000d00: 4a82 ldr r2, [pc, #520] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d02: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
8000d06: 6013 str r3, [r2, #0]
|
|
8000d08: e036 b.n 8000d78 <HAL_RCC_OscConfig+0x19c>
|
|
8000d0a: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8000d0e: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8000d12: 681b ldr r3, [r3, #0]
|
|
8000d14: 685b ldr r3, [r3, #4]
|
|
8000d16: 2b00 cmp r3, #0
|
|
8000d18: d10c bne.n 8000d34 <HAL_RCC_OscConfig+0x158>
|
|
8000d1a: 4b7c ldr r3, [pc, #496] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d1c: 681b ldr r3, [r3, #0]
|
|
8000d1e: 4a7b ldr r2, [pc, #492] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d20: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
8000d24: 6013 str r3, [r2, #0]
|
|
8000d26: 4b79 ldr r3, [pc, #484] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d28: 681b ldr r3, [r3, #0]
|
|
8000d2a: 4a78 ldr r2, [pc, #480] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d2c: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
8000d30: 6013 str r3, [r2, #0]
|
|
8000d32: e021 b.n 8000d78 <HAL_RCC_OscConfig+0x19c>
|
|
8000d34: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8000d38: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8000d3c: 681b ldr r3, [r3, #0]
|
|
8000d3e: 685b ldr r3, [r3, #4]
|
|
8000d40: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
|
|
8000d44: d10c bne.n 8000d60 <HAL_RCC_OscConfig+0x184>
|
|
8000d46: 4b71 ldr r3, [pc, #452] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d48: 681b ldr r3, [r3, #0]
|
|
8000d4a: 4a70 ldr r2, [pc, #448] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d4c: f443 2380 orr.w r3, r3, #262144 ; 0x40000
|
|
8000d50: 6013 str r3, [r2, #0]
|
|
8000d52: 4b6e ldr r3, [pc, #440] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d54: 681b ldr r3, [r3, #0]
|
|
8000d56: 4a6d ldr r2, [pc, #436] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d58: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
8000d5c: 6013 str r3, [r2, #0]
|
|
8000d5e: e00b b.n 8000d78 <HAL_RCC_OscConfig+0x19c>
|
|
8000d60: 4b6a ldr r3, [pc, #424] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d62: 681b ldr r3, [r3, #0]
|
|
8000d64: 4a69 ldr r2, [pc, #420] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d66: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
8000d6a: 6013 str r3, [r2, #0]
|
|
8000d6c: 4b67 ldr r3, [pc, #412] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d6e: 681b ldr r3, [r3, #0]
|
|
8000d70: 4a66 ldr r2, [pc, #408] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d72: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
8000d76: 6013 str r3, [r2, #0]
|
|
|
|
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
|
|
/* Configure the HSE predivision factor --------------------------------*/
|
|
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
|
|
8000d78: 4b64 ldr r3, [pc, #400] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d7a: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8000d7c: f023 020f bic.w r2, r3, #15
|
|
8000d80: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8000d84: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8000d88: 681b ldr r3, [r3, #0]
|
|
8000d8a: 689b ldr r3, [r3, #8]
|
|
8000d8c: 495f ldr r1, [pc, #380] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000d8e: 4313 orrs r3, r2
|
|
8000d90: 62cb str r3, [r1, #44] ; 0x2c
|
|
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
|
|
|
|
/* Check the HSE State */
|
|
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8000d92: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8000d96: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8000d9a: 681b ldr r3, [r3, #0]
|
|
8000d9c: 685b ldr r3, [r3, #4]
|
|
8000d9e: 2b00 cmp r3, #0
|
|
8000da0: d059 beq.n 8000e56 <HAL_RCC_OscConfig+0x27a>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000da2: f7ff fc63 bl 800066c <HAL_GetTick>
|
|
8000da6: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
|
|
|
|
/* Wait till HSE is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8000daa: e00a b.n 8000dc2 <HAL_RCC_OscConfig+0x1e6>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
|
8000dac: f7ff fc5e bl 800066c <HAL_GetTick>
|
|
8000db0: 4602 mov r2, r0
|
|
8000db2: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
|
|
8000db6: 1ad3 subs r3, r2, r3
|
|
8000db8: 2b64 cmp r3, #100 ; 0x64
|
|
8000dba: d902 bls.n 8000dc2 <HAL_RCC_OscConfig+0x1e6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000dbc: 2303 movs r3, #3
|
|
8000dbe: f000 bf43 b.w 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
8000dc2: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8000dc6: f8c7 31d0 str.w r3, [r7, #464] ; 0x1d0
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8000dca: f8d7 31d0 ldr.w r3, [r7, #464] ; 0x1d0
|
|
8000dce: fa93 f3a3 rbit r3, r3
|
|
8000dd2: f8c7 31cc str.w r3, [r7, #460] ; 0x1cc
|
|
return result;
|
|
8000dd6: f8d7 31cc ldr.w r3, [r7, #460] ; 0x1cc
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8000dda: fab3 f383 clz r3, r3
|
|
8000dde: b2db uxtb r3, r3
|
|
8000de0: 095b lsrs r3, r3, #5
|
|
8000de2: b2db uxtb r3, r3
|
|
8000de4: f043 0301 orr.w r3, r3, #1
|
|
8000de8: b2db uxtb r3, r3
|
|
8000dea: 2b01 cmp r3, #1
|
|
8000dec: d102 bne.n 8000df4 <HAL_RCC_OscConfig+0x218>
|
|
8000dee: 4b47 ldr r3, [pc, #284] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000df0: 681b ldr r3, [r3, #0]
|
|
8000df2: e015 b.n 8000e20 <HAL_RCC_OscConfig+0x244>
|
|
8000df4: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8000df8: f8c7 31c8 str.w r3, [r7, #456] ; 0x1c8
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8000dfc: f8d7 31c8 ldr.w r3, [r7, #456] ; 0x1c8
|
|
8000e00: fa93 f3a3 rbit r3, r3
|
|
8000e04: f8c7 31c4 str.w r3, [r7, #452] ; 0x1c4
|
|
8000e08: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8000e0c: f8c7 31c0 str.w r3, [r7, #448] ; 0x1c0
|
|
8000e10: f8d7 31c0 ldr.w r3, [r7, #448] ; 0x1c0
|
|
8000e14: fa93 f3a3 rbit r3, r3
|
|
8000e18: f8c7 31bc str.w r3, [r7, #444] ; 0x1bc
|
|
8000e1c: 4b3b ldr r3, [pc, #236] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000e1e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8000e20: f44f 3200 mov.w r2, #131072 ; 0x20000
|
|
8000e24: f8c7 21b8 str.w r2, [r7, #440] ; 0x1b8
|
|
8000e28: f8d7 21b8 ldr.w r2, [r7, #440] ; 0x1b8
|
|
8000e2c: fa92 f2a2 rbit r2, r2
|
|
8000e30: f8c7 21b4 str.w r2, [r7, #436] ; 0x1b4
|
|
return result;
|
|
8000e34: f8d7 21b4 ldr.w r2, [r7, #436] ; 0x1b4
|
|
8000e38: fab2 f282 clz r2, r2
|
|
8000e3c: b2d2 uxtb r2, r2
|
|
8000e3e: f042 0220 orr.w r2, r2, #32
|
|
8000e42: b2d2 uxtb r2, r2
|
|
8000e44: f002 021f and.w r2, r2, #31
|
|
8000e48: 2101 movs r1, #1
|
|
8000e4a: fa01 f202 lsl.w r2, r1, r2
|
|
8000e4e: 4013 ands r3, r2
|
|
8000e50: 2b00 cmp r3, #0
|
|
8000e52: d0ab beq.n 8000dac <HAL_RCC_OscConfig+0x1d0>
|
|
8000e54: e05d b.n 8000f12 <HAL_RCC_OscConfig+0x336>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000e56: f7ff fc09 bl 800066c <HAL_GetTick>
|
|
8000e5a: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
|
|
|
|
/* Wait till HSE is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8000e5e: e00a b.n 8000e76 <HAL_RCC_OscConfig+0x29a>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
|
8000e60: f7ff fc04 bl 800066c <HAL_GetTick>
|
|
8000e64: 4602 mov r2, r0
|
|
8000e66: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
|
|
8000e6a: 1ad3 subs r3, r2, r3
|
|
8000e6c: 2b64 cmp r3, #100 ; 0x64
|
|
8000e6e: d902 bls.n 8000e76 <HAL_RCC_OscConfig+0x29a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000e70: 2303 movs r3, #3
|
|
8000e72: f000 bee9 b.w 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
8000e76: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8000e7a: f8c7 31b0 str.w r3, [r7, #432] ; 0x1b0
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8000e7e: f8d7 31b0 ldr.w r3, [r7, #432] ; 0x1b0
|
|
8000e82: fa93 f3a3 rbit r3, r3
|
|
8000e86: f8c7 31ac str.w r3, [r7, #428] ; 0x1ac
|
|
return result;
|
|
8000e8a: f8d7 31ac ldr.w r3, [r7, #428] ; 0x1ac
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8000e8e: fab3 f383 clz r3, r3
|
|
8000e92: b2db uxtb r3, r3
|
|
8000e94: 095b lsrs r3, r3, #5
|
|
8000e96: b2db uxtb r3, r3
|
|
8000e98: f043 0301 orr.w r3, r3, #1
|
|
8000e9c: b2db uxtb r3, r3
|
|
8000e9e: 2b01 cmp r3, #1
|
|
8000ea0: d102 bne.n 8000ea8 <HAL_RCC_OscConfig+0x2cc>
|
|
8000ea2: 4b1a ldr r3, [pc, #104] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000ea4: 681b ldr r3, [r3, #0]
|
|
8000ea6: e015 b.n 8000ed4 <HAL_RCC_OscConfig+0x2f8>
|
|
8000ea8: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8000eac: f8c7 31a8 str.w r3, [r7, #424] ; 0x1a8
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8000eb0: f8d7 31a8 ldr.w r3, [r7, #424] ; 0x1a8
|
|
8000eb4: fa93 f3a3 rbit r3, r3
|
|
8000eb8: f8c7 31a4 str.w r3, [r7, #420] ; 0x1a4
|
|
8000ebc: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8000ec0: f8c7 31a0 str.w r3, [r7, #416] ; 0x1a0
|
|
8000ec4: f8d7 31a0 ldr.w r3, [r7, #416] ; 0x1a0
|
|
8000ec8: fa93 f3a3 rbit r3, r3
|
|
8000ecc: f8c7 319c str.w r3, [r7, #412] ; 0x19c
|
|
8000ed0: 4b0e ldr r3, [pc, #56] ; (8000f0c <HAL_RCC_OscConfig+0x330>)
|
|
8000ed2: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8000ed4: f44f 3200 mov.w r2, #131072 ; 0x20000
|
|
8000ed8: f8c7 2198 str.w r2, [r7, #408] ; 0x198
|
|
8000edc: f8d7 2198 ldr.w r2, [r7, #408] ; 0x198
|
|
8000ee0: fa92 f2a2 rbit r2, r2
|
|
8000ee4: f8c7 2194 str.w r2, [r7, #404] ; 0x194
|
|
return result;
|
|
8000ee8: f8d7 2194 ldr.w r2, [r7, #404] ; 0x194
|
|
8000eec: fab2 f282 clz r2, r2
|
|
8000ef0: b2d2 uxtb r2, r2
|
|
8000ef2: f042 0220 orr.w r2, r2, #32
|
|
8000ef6: b2d2 uxtb r2, r2
|
|
8000ef8: f002 021f and.w r2, r2, #31
|
|
8000efc: 2101 movs r1, #1
|
|
8000efe: fa01 f202 lsl.w r2, r1, r2
|
|
8000f02: 4013 ands r3, r2
|
|
8000f04: 2b00 cmp r3, #0
|
|
8000f06: d1ab bne.n 8000e60 <HAL_RCC_OscConfig+0x284>
|
|
8000f08: e003 b.n 8000f12 <HAL_RCC_OscConfig+0x336>
|
|
8000f0a: bf00 nop
|
|
8000f0c: 40021000 .word 0x40021000
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8000f10: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8000f12: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8000f16: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8000f1a: 681b ldr r3, [r3, #0]
|
|
8000f1c: 681b ldr r3, [r3, #0]
|
|
8000f1e: f003 0302 and.w r3, r3, #2
|
|
8000f22: 2b00 cmp r3, #0
|
|
8000f24: f000 817d beq.w 8001222 <HAL_RCC_OscConfig+0x646>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
8000f28: 4ba6 ldr r3, [pc, #664] ; (80011c4 <HAL_RCC_OscConfig+0x5e8>)
|
|
8000f2a: 685b ldr r3, [r3, #4]
|
|
8000f2c: f003 030c and.w r3, r3, #12
|
|
8000f30: 2b00 cmp r3, #0
|
|
8000f32: d00b beq.n 8000f4c <HAL_RCC_OscConfig+0x370>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
|
|
8000f34: 4ba3 ldr r3, [pc, #652] ; (80011c4 <HAL_RCC_OscConfig+0x5e8>)
|
|
8000f36: 685b ldr r3, [r3, #4]
|
|
8000f38: f003 030c and.w r3, r3, #12
|
|
8000f3c: 2b08 cmp r3, #8
|
|
8000f3e: d172 bne.n 8001026 <HAL_RCC_OscConfig+0x44a>
|
|
8000f40: 4ba0 ldr r3, [pc, #640] ; (80011c4 <HAL_RCC_OscConfig+0x5e8>)
|
|
8000f42: 685b ldr r3, [r3, #4]
|
|
8000f44: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8000f48: 2b00 cmp r3, #0
|
|
8000f4a: d16c bne.n 8001026 <HAL_RCC_OscConfig+0x44a>
|
|
8000f4c: 2302 movs r3, #2
|
|
8000f4e: f8c7 3190 str.w r3, [r7, #400] ; 0x190
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8000f52: f8d7 3190 ldr.w r3, [r7, #400] ; 0x190
|
|
8000f56: fa93 f3a3 rbit r3, r3
|
|
8000f5a: f8c7 318c str.w r3, [r7, #396] ; 0x18c
|
|
return result;
|
|
8000f5e: f8d7 318c ldr.w r3, [r7, #396] ; 0x18c
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8000f62: fab3 f383 clz r3, r3
|
|
8000f66: b2db uxtb r3, r3
|
|
8000f68: 095b lsrs r3, r3, #5
|
|
8000f6a: b2db uxtb r3, r3
|
|
8000f6c: f043 0301 orr.w r3, r3, #1
|
|
8000f70: b2db uxtb r3, r3
|
|
8000f72: 2b01 cmp r3, #1
|
|
8000f74: d102 bne.n 8000f7c <HAL_RCC_OscConfig+0x3a0>
|
|
8000f76: 4b93 ldr r3, [pc, #588] ; (80011c4 <HAL_RCC_OscConfig+0x5e8>)
|
|
8000f78: 681b ldr r3, [r3, #0]
|
|
8000f7a: e013 b.n 8000fa4 <HAL_RCC_OscConfig+0x3c8>
|
|
8000f7c: 2302 movs r3, #2
|
|
8000f7e: f8c7 3188 str.w r3, [r7, #392] ; 0x188
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8000f82: f8d7 3188 ldr.w r3, [r7, #392] ; 0x188
|
|
8000f86: fa93 f3a3 rbit r3, r3
|
|
8000f8a: f8c7 3184 str.w r3, [r7, #388] ; 0x184
|
|
8000f8e: 2302 movs r3, #2
|
|
8000f90: f8c7 3180 str.w r3, [r7, #384] ; 0x180
|
|
8000f94: f8d7 3180 ldr.w r3, [r7, #384] ; 0x180
|
|
8000f98: fa93 f3a3 rbit r3, r3
|
|
8000f9c: f8c7 317c str.w r3, [r7, #380] ; 0x17c
|
|
8000fa0: 4b88 ldr r3, [pc, #544] ; (80011c4 <HAL_RCC_OscConfig+0x5e8>)
|
|
8000fa2: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8000fa4: 2202 movs r2, #2
|
|
8000fa6: f8c7 2178 str.w r2, [r7, #376] ; 0x178
|
|
8000faa: f8d7 2178 ldr.w r2, [r7, #376] ; 0x178
|
|
8000fae: fa92 f2a2 rbit r2, r2
|
|
8000fb2: f8c7 2174 str.w r2, [r7, #372] ; 0x174
|
|
return result;
|
|
8000fb6: f8d7 2174 ldr.w r2, [r7, #372] ; 0x174
|
|
8000fba: fab2 f282 clz r2, r2
|
|
8000fbe: b2d2 uxtb r2, r2
|
|
8000fc0: f042 0220 orr.w r2, r2, #32
|
|
8000fc4: b2d2 uxtb r2, r2
|
|
8000fc6: f002 021f and.w r2, r2, #31
|
|
8000fca: 2101 movs r1, #1
|
|
8000fcc: fa01 f202 lsl.w r2, r1, r2
|
|
8000fd0: 4013 ands r3, r2
|
|
8000fd2: 2b00 cmp r3, #0
|
|
8000fd4: d00a beq.n 8000fec <HAL_RCC_OscConfig+0x410>
|
|
8000fd6: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8000fda: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8000fde: 681b ldr r3, [r3, #0]
|
|
8000fe0: 691b ldr r3, [r3, #16]
|
|
8000fe2: 2b01 cmp r3, #1
|
|
8000fe4: d002 beq.n 8000fec <HAL_RCC_OscConfig+0x410>
|
|
{
|
|
return HAL_ERROR;
|
|
8000fe6: 2301 movs r3, #1
|
|
8000fe8: f000 be2e b.w 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8000fec: 4b75 ldr r3, [pc, #468] ; (80011c4 <HAL_RCC_OscConfig+0x5e8>)
|
|
8000fee: 681b ldr r3, [r3, #0]
|
|
8000ff0: f023 02f8 bic.w r2, r3, #248 ; 0xf8
|
|
8000ff4: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8000ff8: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8000ffc: 681b ldr r3, [r3, #0]
|
|
8000ffe: 695b ldr r3, [r3, #20]
|
|
8001000: 21f8 movs r1, #248 ; 0xf8
|
|
8001002: f8c7 1170 str.w r1, [r7, #368] ; 0x170
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001006: f8d7 1170 ldr.w r1, [r7, #368] ; 0x170
|
|
800100a: fa91 f1a1 rbit r1, r1
|
|
800100e: f8c7 116c str.w r1, [r7, #364] ; 0x16c
|
|
return result;
|
|
8001012: f8d7 116c ldr.w r1, [r7, #364] ; 0x16c
|
|
8001016: fab1 f181 clz r1, r1
|
|
800101a: b2c9 uxtb r1, r1
|
|
800101c: 408b lsls r3, r1
|
|
800101e: 4969 ldr r1, [pc, #420] ; (80011c4 <HAL_RCC_OscConfig+0x5e8>)
|
|
8001020: 4313 orrs r3, r2
|
|
8001022: 600b str r3, [r1, #0]
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8001024: e0fd b.n 8001222 <HAL_RCC_OscConfig+0x646>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8001026: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800102a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
800102e: 681b ldr r3, [r3, #0]
|
|
8001030: 691b ldr r3, [r3, #16]
|
|
8001032: 2b00 cmp r3, #0
|
|
8001034: f000 8088 beq.w 8001148 <HAL_RCC_OscConfig+0x56c>
|
|
8001038: 2301 movs r3, #1
|
|
800103a: f8c7 3168 str.w r3, [r7, #360] ; 0x168
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800103e: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
|
|
8001042: fa93 f3a3 rbit r3, r3
|
|
8001046: f8c7 3164 str.w r3, [r7, #356] ; 0x164
|
|
return result;
|
|
800104a: f8d7 3164 ldr.w r3, [r7, #356] ; 0x164
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
800104e: fab3 f383 clz r3, r3
|
|
8001052: b2db uxtb r3, r3
|
|
8001054: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
|
|
8001058: f503 1384 add.w r3, r3, #1081344 ; 0x108000
|
|
800105c: 009b lsls r3, r3, #2
|
|
800105e: 461a mov r2, r3
|
|
8001060: 2301 movs r3, #1
|
|
8001062: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001064: f7ff fb02 bl 800066c <HAL_GetTick>
|
|
8001068: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
|
|
|
|
/* Wait till HSI is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
800106c: e00a b.n 8001084 <HAL_RCC_OscConfig+0x4a8>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
|
800106e: f7ff fafd bl 800066c <HAL_GetTick>
|
|
8001072: 4602 mov r2, r0
|
|
8001074: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
|
|
8001078: 1ad3 subs r3, r2, r3
|
|
800107a: 2b02 cmp r3, #2
|
|
800107c: d902 bls.n 8001084 <HAL_RCC_OscConfig+0x4a8>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800107e: 2303 movs r3, #3
|
|
8001080: f000 bde2 b.w 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
8001084: 2302 movs r3, #2
|
|
8001086: f8c7 3160 str.w r3, [r7, #352] ; 0x160
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800108a: f8d7 3160 ldr.w r3, [r7, #352] ; 0x160
|
|
800108e: fa93 f3a3 rbit r3, r3
|
|
8001092: f8c7 315c str.w r3, [r7, #348] ; 0x15c
|
|
return result;
|
|
8001096: f8d7 315c ldr.w r3, [r7, #348] ; 0x15c
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
800109a: fab3 f383 clz r3, r3
|
|
800109e: b2db uxtb r3, r3
|
|
80010a0: 095b lsrs r3, r3, #5
|
|
80010a2: b2db uxtb r3, r3
|
|
80010a4: f043 0301 orr.w r3, r3, #1
|
|
80010a8: b2db uxtb r3, r3
|
|
80010aa: 2b01 cmp r3, #1
|
|
80010ac: d102 bne.n 80010b4 <HAL_RCC_OscConfig+0x4d8>
|
|
80010ae: 4b45 ldr r3, [pc, #276] ; (80011c4 <HAL_RCC_OscConfig+0x5e8>)
|
|
80010b0: 681b ldr r3, [r3, #0]
|
|
80010b2: e013 b.n 80010dc <HAL_RCC_OscConfig+0x500>
|
|
80010b4: 2302 movs r3, #2
|
|
80010b6: f8c7 3158 str.w r3, [r7, #344] ; 0x158
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80010ba: f8d7 3158 ldr.w r3, [r7, #344] ; 0x158
|
|
80010be: fa93 f3a3 rbit r3, r3
|
|
80010c2: f8c7 3154 str.w r3, [r7, #340] ; 0x154
|
|
80010c6: 2302 movs r3, #2
|
|
80010c8: f8c7 3150 str.w r3, [r7, #336] ; 0x150
|
|
80010cc: f8d7 3150 ldr.w r3, [r7, #336] ; 0x150
|
|
80010d0: fa93 f3a3 rbit r3, r3
|
|
80010d4: f8c7 314c str.w r3, [r7, #332] ; 0x14c
|
|
80010d8: 4b3a ldr r3, [pc, #232] ; (80011c4 <HAL_RCC_OscConfig+0x5e8>)
|
|
80010da: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80010dc: 2202 movs r2, #2
|
|
80010de: f8c7 2148 str.w r2, [r7, #328] ; 0x148
|
|
80010e2: f8d7 2148 ldr.w r2, [r7, #328] ; 0x148
|
|
80010e6: fa92 f2a2 rbit r2, r2
|
|
80010ea: f8c7 2144 str.w r2, [r7, #324] ; 0x144
|
|
return result;
|
|
80010ee: f8d7 2144 ldr.w r2, [r7, #324] ; 0x144
|
|
80010f2: fab2 f282 clz r2, r2
|
|
80010f6: b2d2 uxtb r2, r2
|
|
80010f8: f042 0220 orr.w r2, r2, #32
|
|
80010fc: b2d2 uxtb r2, r2
|
|
80010fe: f002 021f and.w r2, r2, #31
|
|
8001102: 2101 movs r1, #1
|
|
8001104: fa01 f202 lsl.w r2, r1, r2
|
|
8001108: 4013 ands r3, r2
|
|
800110a: 2b00 cmp r3, #0
|
|
800110c: d0af beq.n 800106e <HAL_RCC_OscConfig+0x492>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
800110e: 4b2d ldr r3, [pc, #180] ; (80011c4 <HAL_RCC_OscConfig+0x5e8>)
|
|
8001110: 681b ldr r3, [r3, #0]
|
|
8001112: f023 02f8 bic.w r2, r3, #248 ; 0xf8
|
|
8001116: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800111a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
800111e: 681b ldr r3, [r3, #0]
|
|
8001120: 695b ldr r3, [r3, #20]
|
|
8001122: 21f8 movs r1, #248 ; 0xf8
|
|
8001124: f8c7 1140 str.w r1, [r7, #320] ; 0x140
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001128: f8d7 1140 ldr.w r1, [r7, #320] ; 0x140
|
|
800112c: fa91 f1a1 rbit r1, r1
|
|
8001130: f8c7 113c str.w r1, [r7, #316] ; 0x13c
|
|
return result;
|
|
8001134: f8d7 113c ldr.w r1, [r7, #316] ; 0x13c
|
|
8001138: fab1 f181 clz r1, r1
|
|
800113c: b2c9 uxtb r1, r1
|
|
800113e: 408b lsls r3, r1
|
|
8001140: 4920 ldr r1, [pc, #128] ; (80011c4 <HAL_RCC_OscConfig+0x5e8>)
|
|
8001142: 4313 orrs r3, r2
|
|
8001144: 600b str r3, [r1, #0]
|
|
8001146: e06c b.n 8001222 <HAL_RCC_OscConfig+0x646>
|
|
8001148: 2301 movs r3, #1
|
|
800114a: f8c7 3138 str.w r3, [r7, #312] ; 0x138
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800114e: f8d7 3138 ldr.w r3, [r7, #312] ; 0x138
|
|
8001152: fa93 f3a3 rbit r3, r3
|
|
8001156: f8c7 3134 str.w r3, [r7, #308] ; 0x134
|
|
return result;
|
|
800115a: f8d7 3134 ldr.w r3, [r7, #308] ; 0x134
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
800115e: fab3 f383 clz r3, r3
|
|
8001162: b2db uxtb r3, r3
|
|
8001164: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
|
|
8001168: f503 1384 add.w r3, r3, #1081344 ; 0x108000
|
|
800116c: 009b lsls r3, r3, #2
|
|
800116e: 461a mov r2, r3
|
|
8001170: 2300 movs r3, #0
|
|
8001172: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001174: f7ff fa7a bl 800066c <HAL_GetTick>
|
|
8001178: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
|
|
|
|
/* Wait till HSI is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
800117c: e00a b.n 8001194 <HAL_RCC_OscConfig+0x5b8>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
|
800117e: f7ff fa75 bl 800066c <HAL_GetTick>
|
|
8001182: 4602 mov r2, r0
|
|
8001184: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
|
|
8001188: 1ad3 subs r3, r2, r3
|
|
800118a: 2b02 cmp r3, #2
|
|
800118c: d902 bls.n 8001194 <HAL_RCC_OscConfig+0x5b8>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800118e: 2303 movs r3, #3
|
|
8001190: f000 bd5a b.w 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
8001194: 2302 movs r3, #2
|
|
8001196: f8c7 3130 str.w r3, [r7, #304] ; 0x130
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800119a: f8d7 3130 ldr.w r3, [r7, #304] ; 0x130
|
|
800119e: fa93 f3a3 rbit r3, r3
|
|
80011a2: f8c7 312c str.w r3, [r7, #300] ; 0x12c
|
|
return result;
|
|
80011a6: f8d7 312c ldr.w r3, [r7, #300] ; 0x12c
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
80011aa: fab3 f383 clz r3, r3
|
|
80011ae: b2db uxtb r3, r3
|
|
80011b0: 095b lsrs r3, r3, #5
|
|
80011b2: b2db uxtb r3, r3
|
|
80011b4: f043 0301 orr.w r3, r3, #1
|
|
80011b8: b2db uxtb r3, r3
|
|
80011ba: 2b01 cmp r3, #1
|
|
80011bc: d104 bne.n 80011c8 <HAL_RCC_OscConfig+0x5ec>
|
|
80011be: 4b01 ldr r3, [pc, #4] ; (80011c4 <HAL_RCC_OscConfig+0x5e8>)
|
|
80011c0: 681b ldr r3, [r3, #0]
|
|
80011c2: e015 b.n 80011f0 <HAL_RCC_OscConfig+0x614>
|
|
80011c4: 40021000 .word 0x40021000
|
|
80011c8: 2302 movs r3, #2
|
|
80011ca: f8c7 3128 str.w r3, [r7, #296] ; 0x128
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80011ce: f8d7 3128 ldr.w r3, [r7, #296] ; 0x128
|
|
80011d2: fa93 f3a3 rbit r3, r3
|
|
80011d6: f8c7 3124 str.w r3, [r7, #292] ; 0x124
|
|
80011da: 2302 movs r3, #2
|
|
80011dc: f8c7 3120 str.w r3, [r7, #288] ; 0x120
|
|
80011e0: f8d7 3120 ldr.w r3, [r7, #288] ; 0x120
|
|
80011e4: fa93 f3a3 rbit r3, r3
|
|
80011e8: f8c7 311c str.w r3, [r7, #284] ; 0x11c
|
|
80011ec: 4bc8 ldr r3, [pc, #800] ; (8001510 <HAL_RCC_OscConfig+0x934>)
|
|
80011ee: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80011f0: 2202 movs r2, #2
|
|
80011f2: f8c7 2118 str.w r2, [r7, #280] ; 0x118
|
|
80011f6: f8d7 2118 ldr.w r2, [r7, #280] ; 0x118
|
|
80011fa: fa92 f2a2 rbit r2, r2
|
|
80011fe: f8c7 2114 str.w r2, [r7, #276] ; 0x114
|
|
return result;
|
|
8001202: f8d7 2114 ldr.w r2, [r7, #276] ; 0x114
|
|
8001206: fab2 f282 clz r2, r2
|
|
800120a: b2d2 uxtb r2, r2
|
|
800120c: f042 0220 orr.w r2, r2, #32
|
|
8001210: b2d2 uxtb r2, r2
|
|
8001212: f002 021f and.w r2, r2, #31
|
|
8001216: 2101 movs r1, #1
|
|
8001218: fa01 f202 lsl.w r2, r1, r2
|
|
800121c: 4013 ands r3, r2
|
|
800121e: 2b00 cmp r3, #0
|
|
8001220: d1ad bne.n 800117e <HAL_RCC_OscConfig+0x5a2>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8001222: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001226: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
800122a: 681b ldr r3, [r3, #0]
|
|
800122c: 681b ldr r3, [r3, #0]
|
|
800122e: f003 0308 and.w r3, r3, #8
|
|
8001232: 2b00 cmp r3, #0
|
|
8001234: f000 8110 beq.w 8001458 <HAL_RCC_OscConfig+0x87c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8001238: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800123c: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8001240: 681b ldr r3, [r3, #0]
|
|
8001242: 699b ldr r3, [r3, #24]
|
|
8001244: 2b00 cmp r3, #0
|
|
8001246: d079 beq.n 800133c <HAL_RCC_OscConfig+0x760>
|
|
8001248: 2301 movs r3, #1
|
|
800124a: f8c7 3110 str.w r3, [r7, #272] ; 0x110
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800124e: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110
|
|
8001252: fa93 f3a3 rbit r3, r3
|
|
8001256: f8c7 310c str.w r3, [r7, #268] ; 0x10c
|
|
return result;
|
|
800125a: f8d7 310c ldr.w r3, [r7, #268] ; 0x10c
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
800125e: fab3 f383 clz r3, r3
|
|
8001262: b2db uxtb r3, r3
|
|
8001264: 461a mov r2, r3
|
|
8001266: 4bab ldr r3, [pc, #684] ; (8001514 <HAL_RCC_OscConfig+0x938>)
|
|
8001268: 4413 add r3, r2
|
|
800126a: 009b lsls r3, r3, #2
|
|
800126c: 461a mov r2, r3
|
|
800126e: 2301 movs r3, #1
|
|
8001270: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001272: f7ff f9fb bl 800066c <HAL_GetTick>
|
|
8001276: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
|
|
|
|
/* Wait till LSI is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
800127a: e00a b.n 8001292 <HAL_RCC_OscConfig+0x6b6>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
|
800127c: f7ff f9f6 bl 800066c <HAL_GetTick>
|
|
8001280: 4602 mov r2, r0
|
|
8001282: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
|
|
8001286: 1ad3 subs r3, r2, r3
|
|
8001288: 2b02 cmp r3, #2
|
|
800128a: d902 bls.n 8001292 <HAL_RCC_OscConfig+0x6b6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800128c: 2303 movs r3, #3
|
|
800128e: f000 bcdb b.w 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
8001292: 2302 movs r3, #2
|
|
8001294: f8c7 3108 str.w r3, [r7, #264] ; 0x108
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001298: f8d7 3108 ldr.w r3, [r7, #264] ; 0x108
|
|
800129c: fa93 f3a3 rbit r3, r3
|
|
80012a0: f8c7 3104 str.w r3, [r7, #260] ; 0x104
|
|
80012a4: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80012a8: f5a3 7380 sub.w r3, r3, #256 ; 0x100
|
|
80012ac: 2202 movs r2, #2
|
|
80012ae: 601a str r2, [r3, #0]
|
|
80012b0: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80012b4: f5a3 7380 sub.w r3, r3, #256 ; 0x100
|
|
80012b8: 681b ldr r3, [r3, #0]
|
|
80012ba: fa93 f2a3 rbit r2, r3
|
|
80012be: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80012c2: f5a3 7382 sub.w r3, r3, #260 ; 0x104
|
|
80012c6: 601a str r2, [r3, #0]
|
|
80012c8: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80012cc: f5a3 7384 sub.w r3, r3, #264 ; 0x108
|
|
80012d0: 2202 movs r2, #2
|
|
80012d2: 601a str r2, [r3, #0]
|
|
80012d4: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80012d8: f5a3 7384 sub.w r3, r3, #264 ; 0x108
|
|
80012dc: 681b ldr r3, [r3, #0]
|
|
80012de: fa93 f2a3 rbit r2, r3
|
|
80012e2: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80012e6: f5a3 7386 sub.w r3, r3, #268 ; 0x10c
|
|
80012ea: 601a str r2, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
80012ec: 4b88 ldr r3, [pc, #544] ; (8001510 <HAL_RCC_OscConfig+0x934>)
|
|
80012ee: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
80012f0: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80012f4: f5a3 7388 sub.w r3, r3, #272 ; 0x110
|
|
80012f8: 2102 movs r1, #2
|
|
80012fa: 6019 str r1, [r3, #0]
|
|
80012fc: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001300: f5a3 7388 sub.w r3, r3, #272 ; 0x110
|
|
8001304: 681b ldr r3, [r3, #0]
|
|
8001306: fa93 f1a3 rbit r1, r3
|
|
800130a: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800130e: f5a3 738a sub.w r3, r3, #276 ; 0x114
|
|
8001312: 6019 str r1, [r3, #0]
|
|
return result;
|
|
8001314: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001318: f5a3 738a sub.w r3, r3, #276 ; 0x114
|
|
800131c: 681b ldr r3, [r3, #0]
|
|
800131e: fab3 f383 clz r3, r3
|
|
8001322: b2db uxtb r3, r3
|
|
8001324: f043 0360 orr.w r3, r3, #96 ; 0x60
|
|
8001328: b2db uxtb r3, r3
|
|
800132a: f003 031f and.w r3, r3, #31
|
|
800132e: 2101 movs r1, #1
|
|
8001330: fa01 f303 lsl.w r3, r1, r3
|
|
8001334: 4013 ands r3, r2
|
|
8001336: 2b00 cmp r3, #0
|
|
8001338: d0a0 beq.n 800127c <HAL_RCC_OscConfig+0x6a0>
|
|
800133a: e08d b.n 8001458 <HAL_RCC_OscConfig+0x87c>
|
|
800133c: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001340: f5a3 738c sub.w r3, r3, #280 ; 0x118
|
|
8001344: 2201 movs r2, #1
|
|
8001346: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001348: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800134c: f5a3 738c sub.w r3, r3, #280 ; 0x118
|
|
8001350: 681b ldr r3, [r3, #0]
|
|
8001352: fa93 f2a3 rbit r2, r3
|
|
8001356: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800135a: f5a3 738e sub.w r3, r3, #284 ; 0x11c
|
|
800135e: 601a str r2, [r3, #0]
|
|
return result;
|
|
8001360: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001364: f5a3 738e sub.w r3, r3, #284 ; 0x11c
|
|
8001368: 681b ldr r3, [r3, #0]
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
800136a: fab3 f383 clz r3, r3
|
|
800136e: b2db uxtb r3, r3
|
|
8001370: 461a mov r2, r3
|
|
8001372: 4b68 ldr r3, [pc, #416] ; (8001514 <HAL_RCC_OscConfig+0x938>)
|
|
8001374: 4413 add r3, r2
|
|
8001376: 009b lsls r3, r3, #2
|
|
8001378: 461a mov r2, r3
|
|
800137a: 2300 movs r3, #0
|
|
800137c: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800137e: f7ff f975 bl 800066c <HAL_GetTick>
|
|
8001382: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
|
|
|
|
/* Wait till LSI is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8001386: e00a b.n 800139e <HAL_RCC_OscConfig+0x7c2>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
|
8001388: f7ff f970 bl 800066c <HAL_GetTick>
|
|
800138c: 4602 mov r2, r0
|
|
800138e: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
|
|
8001392: 1ad3 subs r3, r2, r3
|
|
8001394: 2b02 cmp r3, #2
|
|
8001396: d902 bls.n 800139e <HAL_RCC_OscConfig+0x7c2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8001398: 2303 movs r3, #3
|
|
800139a: f000 bc55 b.w 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
800139e: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80013a2: f5a3 7390 sub.w r3, r3, #288 ; 0x120
|
|
80013a6: 2202 movs r2, #2
|
|
80013a8: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80013aa: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80013ae: f5a3 7390 sub.w r3, r3, #288 ; 0x120
|
|
80013b2: 681b ldr r3, [r3, #0]
|
|
80013b4: fa93 f2a3 rbit r2, r3
|
|
80013b8: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80013bc: f5a3 7392 sub.w r3, r3, #292 ; 0x124
|
|
80013c0: 601a str r2, [r3, #0]
|
|
80013c2: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80013c6: f5a3 7394 sub.w r3, r3, #296 ; 0x128
|
|
80013ca: 2202 movs r2, #2
|
|
80013cc: 601a str r2, [r3, #0]
|
|
80013ce: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80013d2: f5a3 7394 sub.w r3, r3, #296 ; 0x128
|
|
80013d6: 681b ldr r3, [r3, #0]
|
|
80013d8: fa93 f2a3 rbit r2, r3
|
|
80013dc: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80013e0: f5a3 7396 sub.w r3, r3, #300 ; 0x12c
|
|
80013e4: 601a str r2, [r3, #0]
|
|
80013e6: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80013ea: f5a3 7398 sub.w r3, r3, #304 ; 0x130
|
|
80013ee: 2202 movs r2, #2
|
|
80013f0: 601a str r2, [r3, #0]
|
|
80013f2: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80013f6: f5a3 7398 sub.w r3, r3, #304 ; 0x130
|
|
80013fa: 681b ldr r3, [r3, #0]
|
|
80013fc: fa93 f2a3 rbit r2, r3
|
|
8001400: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001404: f5a3 739a sub.w r3, r3, #308 ; 0x134
|
|
8001408: 601a str r2, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
800140a: 4b41 ldr r3, [pc, #260] ; (8001510 <HAL_RCC_OscConfig+0x934>)
|
|
800140c: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
800140e: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001412: f5a3 739c sub.w r3, r3, #312 ; 0x138
|
|
8001416: 2102 movs r1, #2
|
|
8001418: 6019 str r1, [r3, #0]
|
|
800141a: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800141e: f5a3 739c sub.w r3, r3, #312 ; 0x138
|
|
8001422: 681b ldr r3, [r3, #0]
|
|
8001424: fa93 f1a3 rbit r1, r3
|
|
8001428: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800142c: f5a3 739e sub.w r3, r3, #316 ; 0x13c
|
|
8001430: 6019 str r1, [r3, #0]
|
|
return result;
|
|
8001432: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001436: f5a3 739e sub.w r3, r3, #316 ; 0x13c
|
|
800143a: 681b ldr r3, [r3, #0]
|
|
800143c: fab3 f383 clz r3, r3
|
|
8001440: b2db uxtb r3, r3
|
|
8001442: f043 0360 orr.w r3, r3, #96 ; 0x60
|
|
8001446: b2db uxtb r3, r3
|
|
8001448: f003 031f and.w r3, r3, #31
|
|
800144c: 2101 movs r1, #1
|
|
800144e: fa01 f303 lsl.w r3, r1, r3
|
|
8001452: 4013 ands r3, r2
|
|
8001454: 2b00 cmp r3, #0
|
|
8001456: d197 bne.n 8001388 <HAL_RCC_OscConfig+0x7ac>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8001458: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800145c: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8001460: 681b ldr r3, [r3, #0]
|
|
8001462: 681b ldr r3, [r3, #0]
|
|
8001464: f003 0304 and.w r3, r3, #4
|
|
8001468: 2b00 cmp r3, #0
|
|
800146a: f000 81a1 beq.w 80017b0 <HAL_RCC_OscConfig+0xbd4>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
800146e: 2300 movs r3, #0
|
|
8001470: f887 31ff strb.w r3, [r7, #511] ; 0x1ff
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8001474: 4b26 ldr r3, [pc, #152] ; (8001510 <HAL_RCC_OscConfig+0x934>)
|
|
8001476: 69db ldr r3, [r3, #28]
|
|
8001478: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
800147c: 2b00 cmp r3, #0
|
|
800147e: d116 bne.n 80014ae <HAL_RCC_OscConfig+0x8d2>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8001480: 4b23 ldr r3, [pc, #140] ; (8001510 <HAL_RCC_OscConfig+0x934>)
|
|
8001482: 69db ldr r3, [r3, #28]
|
|
8001484: 4a22 ldr r2, [pc, #136] ; (8001510 <HAL_RCC_OscConfig+0x934>)
|
|
8001486: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
800148a: 61d3 str r3, [r2, #28]
|
|
800148c: 4b20 ldr r3, [pc, #128] ; (8001510 <HAL_RCC_OscConfig+0x934>)
|
|
800148e: 69db ldr r3, [r3, #28]
|
|
8001490: f003 5280 and.w r2, r3, #268435456 ; 0x10000000
|
|
8001494: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001498: f5a3 73fc sub.w r3, r3, #504 ; 0x1f8
|
|
800149c: 601a str r2, [r3, #0]
|
|
800149e: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80014a2: f5a3 73fc sub.w r3, r3, #504 ; 0x1f8
|
|
80014a6: 681b ldr r3, [r3, #0]
|
|
pwrclkchanged = SET;
|
|
80014a8: 2301 movs r3, #1
|
|
80014aa: f887 31ff strb.w r3, [r7, #511] ; 0x1ff
|
|
}
|
|
|
|
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
80014ae: 4b1a ldr r3, [pc, #104] ; (8001518 <HAL_RCC_OscConfig+0x93c>)
|
|
80014b0: 681b ldr r3, [r3, #0]
|
|
80014b2: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
80014b6: 2b00 cmp r3, #0
|
|
80014b8: d11a bne.n 80014f0 <HAL_RCC_OscConfig+0x914>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
80014ba: 4b17 ldr r3, [pc, #92] ; (8001518 <HAL_RCC_OscConfig+0x93c>)
|
|
80014bc: 681b ldr r3, [r3, #0]
|
|
80014be: 4a16 ldr r2, [pc, #88] ; (8001518 <HAL_RCC_OscConfig+0x93c>)
|
|
80014c0: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
80014c4: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
80014c6: f7ff f8d1 bl 800066c <HAL_GetTick>
|
|
80014ca: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
|
|
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
80014ce: e009 b.n 80014e4 <HAL_RCC_OscConfig+0x908>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
80014d0: f7ff f8cc bl 800066c <HAL_GetTick>
|
|
80014d4: 4602 mov r2, r0
|
|
80014d6: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
|
|
80014da: 1ad3 subs r3, r2, r3
|
|
80014dc: 2b64 cmp r3, #100 ; 0x64
|
|
80014de: d901 bls.n 80014e4 <HAL_RCC_OscConfig+0x908>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80014e0: 2303 movs r3, #3
|
|
80014e2: e3b1 b.n 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
80014e4: 4b0c ldr r3, [pc, #48] ; (8001518 <HAL_RCC_OscConfig+0x93c>)
|
|
80014e6: 681b ldr r3, [r3, #0]
|
|
80014e8: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
80014ec: 2b00 cmp r3, #0
|
|
80014ee: d0ef beq.n 80014d0 <HAL_RCC_OscConfig+0x8f4>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
80014f0: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80014f4: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
80014f8: 681b ldr r3, [r3, #0]
|
|
80014fa: 68db ldr r3, [r3, #12]
|
|
80014fc: 2b01 cmp r3, #1
|
|
80014fe: d10d bne.n 800151c <HAL_RCC_OscConfig+0x940>
|
|
8001500: 4b03 ldr r3, [pc, #12] ; (8001510 <HAL_RCC_OscConfig+0x934>)
|
|
8001502: 6a1b ldr r3, [r3, #32]
|
|
8001504: 4a02 ldr r2, [pc, #8] ; (8001510 <HAL_RCC_OscConfig+0x934>)
|
|
8001506: f043 0301 orr.w r3, r3, #1
|
|
800150a: 6213 str r3, [r2, #32]
|
|
800150c: e03c b.n 8001588 <HAL_RCC_OscConfig+0x9ac>
|
|
800150e: bf00 nop
|
|
8001510: 40021000 .word 0x40021000
|
|
8001514: 10908120 .word 0x10908120
|
|
8001518: 40007000 .word 0x40007000
|
|
800151c: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001520: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8001524: 681b ldr r3, [r3, #0]
|
|
8001526: 68db ldr r3, [r3, #12]
|
|
8001528: 2b00 cmp r3, #0
|
|
800152a: d10c bne.n 8001546 <HAL_RCC_OscConfig+0x96a>
|
|
800152c: 4bc1 ldr r3, [pc, #772] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
800152e: 6a1b ldr r3, [r3, #32]
|
|
8001530: 4ac0 ldr r2, [pc, #768] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
8001532: f023 0301 bic.w r3, r3, #1
|
|
8001536: 6213 str r3, [r2, #32]
|
|
8001538: 4bbe ldr r3, [pc, #760] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
800153a: 6a1b ldr r3, [r3, #32]
|
|
800153c: 4abd ldr r2, [pc, #756] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
800153e: f023 0304 bic.w r3, r3, #4
|
|
8001542: 6213 str r3, [r2, #32]
|
|
8001544: e020 b.n 8001588 <HAL_RCC_OscConfig+0x9ac>
|
|
8001546: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800154a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
800154e: 681b ldr r3, [r3, #0]
|
|
8001550: 68db ldr r3, [r3, #12]
|
|
8001552: 2b05 cmp r3, #5
|
|
8001554: d10c bne.n 8001570 <HAL_RCC_OscConfig+0x994>
|
|
8001556: 4bb7 ldr r3, [pc, #732] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
8001558: 6a1b ldr r3, [r3, #32]
|
|
800155a: 4ab6 ldr r2, [pc, #728] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
800155c: f043 0304 orr.w r3, r3, #4
|
|
8001560: 6213 str r3, [r2, #32]
|
|
8001562: 4bb4 ldr r3, [pc, #720] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
8001564: 6a1b ldr r3, [r3, #32]
|
|
8001566: 4ab3 ldr r2, [pc, #716] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
8001568: f043 0301 orr.w r3, r3, #1
|
|
800156c: 6213 str r3, [r2, #32]
|
|
800156e: e00b b.n 8001588 <HAL_RCC_OscConfig+0x9ac>
|
|
8001570: 4bb0 ldr r3, [pc, #704] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
8001572: 6a1b ldr r3, [r3, #32]
|
|
8001574: 4aaf ldr r2, [pc, #700] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
8001576: f023 0301 bic.w r3, r3, #1
|
|
800157a: 6213 str r3, [r2, #32]
|
|
800157c: 4bad ldr r3, [pc, #692] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
800157e: 6a1b ldr r3, [r3, #32]
|
|
8001580: 4aac ldr r2, [pc, #688] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
8001582: f023 0304 bic.w r3, r3, #4
|
|
8001586: 6213 str r3, [r2, #32]
|
|
/* Check the LSE State */
|
|
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8001588: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800158c: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8001590: 681b ldr r3, [r3, #0]
|
|
8001592: 68db ldr r3, [r3, #12]
|
|
8001594: 2b00 cmp r3, #0
|
|
8001596: f000 8081 beq.w 800169c <HAL_RCC_OscConfig+0xac0>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800159a: f7ff f867 bl 800066c <HAL_GetTick>
|
|
800159e: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
|
|
|
|
/* Wait till LSE is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
80015a2: e00b b.n 80015bc <HAL_RCC_OscConfig+0x9e0>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
80015a4: f7ff f862 bl 800066c <HAL_GetTick>
|
|
80015a8: 4602 mov r2, r0
|
|
80015aa: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
|
|
80015ae: 1ad3 subs r3, r2, r3
|
|
80015b0: f241 3288 movw r2, #5000 ; 0x1388
|
|
80015b4: 4293 cmp r3, r2
|
|
80015b6: d901 bls.n 80015bc <HAL_RCC_OscConfig+0x9e0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80015b8: 2303 movs r3, #3
|
|
80015ba: e345 b.n 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
80015bc: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80015c0: f5a3 73a0 sub.w r3, r3, #320 ; 0x140
|
|
80015c4: 2202 movs r2, #2
|
|
80015c6: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80015c8: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80015cc: f5a3 73a0 sub.w r3, r3, #320 ; 0x140
|
|
80015d0: 681b ldr r3, [r3, #0]
|
|
80015d2: fa93 f2a3 rbit r2, r3
|
|
80015d6: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80015da: f5a3 73a2 sub.w r3, r3, #324 ; 0x144
|
|
80015de: 601a str r2, [r3, #0]
|
|
80015e0: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80015e4: f5a3 73a4 sub.w r3, r3, #328 ; 0x148
|
|
80015e8: 2202 movs r2, #2
|
|
80015ea: 601a str r2, [r3, #0]
|
|
80015ec: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80015f0: f5a3 73a4 sub.w r3, r3, #328 ; 0x148
|
|
80015f4: 681b ldr r3, [r3, #0]
|
|
80015f6: fa93 f2a3 rbit r2, r3
|
|
80015fa: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80015fe: f5a3 73a6 sub.w r3, r3, #332 ; 0x14c
|
|
8001602: 601a str r2, [r3, #0]
|
|
return result;
|
|
8001604: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001608: f5a3 73a6 sub.w r3, r3, #332 ; 0x14c
|
|
800160c: 681b ldr r3, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
800160e: fab3 f383 clz r3, r3
|
|
8001612: b2db uxtb r3, r3
|
|
8001614: 095b lsrs r3, r3, #5
|
|
8001616: b2db uxtb r3, r3
|
|
8001618: f043 0302 orr.w r3, r3, #2
|
|
800161c: b2db uxtb r3, r3
|
|
800161e: 2b02 cmp r3, #2
|
|
8001620: d102 bne.n 8001628 <HAL_RCC_OscConfig+0xa4c>
|
|
8001622: 4b84 ldr r3, [pc, #528] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
8001624: 6a1b ldr r3, [r3, #32]
|
|
8001626: e013 b.n 8001650 <HAL_RCC_OscConfig+0xa74>
|
|
8001628: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800162c: f5a3 73a8 sub.w r3, r3, #336 ; 0x150
|
|
8001630: 2202 movs r2, #2
|
|
8001632: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001634: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001638: f5a3 73a8 sub.w r3, r3, #336 ; 0x150
|
|
800163c: 681b ldr r3, [r3, #0]
|
|
800163e: fa93 f2a3 rbit r2, r3
|
|
8001642: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001646: f5a3 73aa sub.w r3, r3, #340 ; 0x154
|
|
800164a: 601a str r2, [r3, #0]
|
|
800164c: 4b79 ldr r3, [pc, #484] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
800164e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8001650: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001654: f5a2 72ac sub.w r2, r2, #344 ; 0x158
|
|
8001658: 2102 movs r1, #2
|
|
800165a: 6011 str r1, [r2, #0]
|
|
800165c: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001660: f5a2 72ac sub.w r2, r2, #344 ; 0x158
|
|
8001664: 6812 ldr r2, [r2, #0]
|
|
8001666: fa92 f1a2 rbit r1, r2
|
|
800166a: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
800166e: f5a2 72ae sub.w r2, r2, #348 ; 0x15c
|
|
8001672: 6011 str r1, [r2, #0]
|
|
return result;
|
|
8001674: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001678: f5a2 72ae sub.w r2, r2, #348 ; 0x15c
|
|
800167c: 6812 ldr r2, [r2, #0]
|
|
800167e: fab2 f282 clz r2, r2
|
|
8001682: b2d2 uxtb r2, r2
|
|
8001684: f042 0240 orr.w r2, r2, #64 ; 0x40
|
|
8001688: b2d2 uxtb r2, r2
|
|
800168a: f002 021f and.w r2, r2, #31
|
|
800168e: 2101 movs r1, #1
|
|
8001690: fa01 f202 lsl.w r2, r1, r2
|
|
8001694: 4013 ands r3, r2
|
|
8001696: 2b00 cmp r3, #0
|
|
8001698: d084 beq.n 80015a4 <HAL_RCC_OscConfig+0x9c8>
|
|
800169a: e07f b.n 800179c <HAL_RCC_OscConfig+0xbc0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800169c: f7fe ffe6 bl 800066c <HAL_GetTick>
|
|
80016a0: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
|
|
|
|
/* Wait till LSE is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
80016a4: e00b b.n 80016be <HAL_RCC_OscConfig+0xae2>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
80016a6: f7fe ffe1 bl 800066c <HAL_GetTick>
|
|
80016aa: 4602 mov r2, r0
|
|
80016ac: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
|
|
80016b0: 1ad3 subs r3, r2, r3
|
|
80016b2: f241 3288 movw r2, #5000 ; 0x1388
|
|
80016b6: 4293 cmp r3, r2
|
|
80016b8: d901 bls.n 80016be <HAL_RCC_OscConfig+0xae2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80016ba: 2303 movs r3, #3
|
|
80016bc: e2c4 b.n 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
80016be: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80016c2: f5a3 73b0 sub.w r3, r3, #352 ; 0x160
|
|
80016c6: 2202 movs r2, #2
|
|
80016c8: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80016ca: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80016ce: f5a3 73b0 sub.w r3, r3, #352 ; 0x160
|
|
80016d2: 681b ldr r3, [r3, #0]
|
|
80016d4: fa93 f2a3 rbit r2, r3
|
|
80016d8: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80016dc: f5a3 73b2 sub.w r3, r3, #356 ; 0x164
|
|
80016e0: 601a str r2, [r3, #0]
|
|
80016e2: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80016e6: f5a3 73b4 sub.w r3, r3, #360 ; 0x168
|
|
80016ea: 2202 movs r2, #2
|
|
80016ec: 601a str r2, [r3, #0]
|
|
80016ee: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80016f2: f5a3 73b4 sub.w r3, r3, #360 ; 0x168
|
|
80016f6: 681b ldr r3, [r3, #0]
|
|
80016f8: fa93 f2a3 rbit r2, r3
|
|
80016fc: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001700: f5a3 73b6 sub.w r3, r3, #364 ; 0x16c
|
|
8001704: 601a str r2, [r3, #0]
|
|
return result;
|
|
8001706: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800170a: f5a3 73b6 sub.w r3, r3, #364 ; 0x16c
|
|
800170e: 681b ldr r3, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8001710: fab3 f383 clz r3, r3
|
|
8001714: b2db uxtb r3, r3
|
|
8001716: 095b lsrs r3, r3, #5
|
|
8001718: b2db uxtb r3, r3
|
|
800171a: f043 0302 orr.w r3, r3, #2
|
|
800171e: b2db uxtb r3, r3
|
|
8001720: 2b02 cmp r3, #2
|
|
8001722: d102 bne.n 800172a <HAL_RCC_OscConfig+0xb4e>
|
|
8001724: 4b43 ldr r3, [pc, #268] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
8001726: 6a1b ldr r3, [r3, #32]
|
|
8001728: e013 b.n 8001752 <HAL_RCC_OscConfig+0xb76>
|
|
800172a: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800172e: f5a3 73b8 sub.w r3, r3, #368 ; 0x170
|
|
8001732: 2202 movs r2, #2
|
|
8001734: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001736: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800173a: f5a3 73b8 sub.w r3, r3, #368 ; 0x170
|
|
800173e: 681b ldr r3, [r3, #0]
|
|
8001740: fa93 f2a3 rbit r2, r3
|
|
8001744: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001748: f5a3 73ba sub.w r3, r3, #372 ; 0x174
|
|
800174c: 601a str r2, [r3, #0]
|
|
800174e: 4b39 ldr r3, [pc, #228] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
8001750: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8001752: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001756: f5a2 72bc sub.w r2, r2, #376 ; 0x178
|
|
800175a: 2102 movs r1, #2
|
|
800175c: 6011 str r1, [r2, #0]
|
|
800175e: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001762: f5a2 72bc sub.w r2, r2, #376 ; 0x178
|
|
8001766: 6812 ldr r2, [r2, #0]
|
|
8001768: fa92 f1a2 rbit r1, r2
|
|
800176c: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001770: f5a2 72be sub.w r2, r2, #380 ; 0x17c
|
|
8001774: 6011 str r1, [r2, #0]
|
|
return result;
|
|
8001776: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
800177a: f5a2 72be sub.w r2, r2, #380 ; 0x17c
|
|
800177e: 6812 ldr r2, [r2, #0]
|
|
8001780: fab2 f282 clz r2, r2
|
|
8001784: b2d2 uxtb r2, r2
|
|
8001786: f042 0240 orr.w r2, r2, #64 ; 0x40
|
|
800178a: b2d2 uxtb r2, r2
|
|
800178c: f002 021f and.w r2, r2, #31
|
|
8001790: 2101 movs r1, #1
|
|
8001792: fa01 f202 lsl.w r2, r1, r2
|
|
8001796: 4013 ands r3, r2
|
|
8001798: 2b00 cmp r3, #0
|
|
800179a: d184 bne.n 80016a6 <HAL_RCC_OscConfig+0xaca>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if(pwrclkchanged == SET)
|
|
800179c: f897 31ff ldrb.w r3, [r7, #511] ; 0x1ff
|
|
80017a0: 2b01 cmp r3, #1
|
|
80017a2: d105 bne.n 80017b0 <HAL_RCC_OscConfig+0xbd4>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
80017a4: 4b23 ldr r3, [pc, #140] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
80017a6: 69db ldr r3, [r3, #28]
|
|
80017a8: 4a22 ldr r2, [pc, #136] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
80017aa: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
|
80017ae: 61d3 str r3, [r2, #28]
|
|
}
|
|
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
80017b0: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80017b4: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
80017b8: 681b ldr r3, [r3, #0]
|
|
80017ba: 69db ldr r3, [r3, #28]
|
|
80017bc: 2b00 cmp r3, #0
|
|
80017be: f000 8242 beq.w 8001c46 <HAL_RCC_OscConfig+0x106a>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
80017c2: 4b1c ldr r3, [pc, #112] ; (8001834 <HAL_RCC_OscConfig+0xc58>)
|
|
80017c4: 685b ldr r3, [r3, #4]
|
|
80017c6: f003 030c and.w r3, r3, #12
|
|
80017ca: 2b08 cmp r3, #8
|
|
80017cc: f000 8213 beq.w 8001bf6 <HAL_RCC_OscConfig+0x101a>
|
|
{
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
80017d0: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80017d4: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
80017d8: 681b ldr r3, [r3, #0]
|
|
80017da: 69db ldr r3, [r3, #28]
|
|
80017dc: 2b02 cmp r3, #2
|
|
80017de: f040 8162 bne.w 8001aa6 <HAL_RCC_OscConfig+0xeca>
|
|
80017e2: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80017e6: f5a3 73c0 sub.w r3, r3, #384 ; 0x180
|
|
80017ea: f04f 7280 mov.w r2, #16777216 ; 0x1000000
|
|
80017ee: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80017f0: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80017f4: f5a3 73c0 sub.w r3, r3, #384 ; 0x180
|
|
80017f8: 681b ldr r3, [r3, #0]
|
|
80017fa: fa93 f2a3 rbit r2, r3
|
|
80017fe: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001802: f5a3 73c2 sub.w r3, r3, #388 ; 0x184
|
|
8001806: 601a str r2, [r3, #0]
|
|
return result;
|
|
8001808: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800180c: f5a3 73c2 sub.w r3, r3, #388 ; 0x184
|
|
8001810: 681b ldr r3, [r3, #0]
|
|
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
|
|
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
|
|
#endif
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8001812: fab3 f383 clz r3, r3
|
|
8001816: b2db uxtb r3, r3
|
|
8001818: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
|
|
800181c: f503 1384 add.w r3, r3, #1081344 ; 0x108000
|
|
8001820: 009b lsls r3, r3, #2
|
|
8001822: 461a mov r2, r3
|
|
8001824: 2300 movs r3, #0
|
|
8001826: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001828: f7fe ff20 bl 800066c <HAL_GetTick>
|
|
800182c: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8001830: e00c b.n 800184c <HAL_RCC_OscConfig+0xc70>
|
|
8001832: bf00 nop
|
|
8001834: 40021000 .word 0x40021000
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
8001838: f7fe ff18 bl 800066c <HAL_GetTick>
|
|
800183c: 4602 mov r2, r0
|
|
800183e: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
|
|
8001842: 1ad3 subs r3, r2, r3
|
|
8001844: 2b02 cmp r3, #2
|
|
8001846: d901 bls.n 800184c <HAL_RCC_OscConfig+0xc70>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8001848: 2303 movs r3, #3
|
|
800184a: e1fd b.n 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
800184c: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001850: f5a3 73c4 sub.w r3, r3, #392 ; 0x188
|
|
8001854: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
8001858: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800185a: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800185e: f5a3 73c4 sub.w r3, r3, #392 ; 0x188
|
|
8001862: 681b ldr r3, [r3, #0]
|
|
8001864: fa93 f2a3 rbit r2, r3
|
|
8001868: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800186c: f5a3 73c6 sub.w r3, r3, #396 ; 0x18c
|
|
8001870: 601a str r2, [r3, #0]
|
|
return result;
|
|
8001872: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001876: f5a3 73c6 sub.w r3, r3, #396 ; 0x18c
|
|
800187a: 681b ldr r3, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
800187c: fab3 f383 clz r3, r3
|
|
8001880: b2db uxtb r3, r3
|
|
8001882: 095b lsrs r3, r3, #5
|
|
8001884: b2db uxtb r3, r3
|
|
8001886: f043 0301 orr.w r3, r3, #1
|
|
800188a: b2db uxtb r3, r3
|
|
800188c: 2b01 cmp r3, #1
|
|
800188e: d102 bne.n 8001896 <HAL_RCC_OscConfig+0xcba>
|
|
8001890: 4bb0 ldr r3, [pc, #704] ; (8001b54 <HAL_RCC_OscConfig+0xf78>)
|
|
8001892: 681b ldr r3, [r3, #0]
|
|
8001894: e027 b.n 80018e6 <HAL_RCC_OscConfig+0xd0a>
|
|
8001896: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800189a: f5a3 73c8 sub.w r3, r3, #400 ; 0x190
|
|
800189e: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
80018a2: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80018a4: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80018a8: f5a3 73c8 sub.w r3, r3, #400 ; 0x190
|
|
80018ac: 681b ldr r3, [r3, #0]
|
|
80018ae: fa93 f2a3 rbit r2, r3
|
|
80018b2: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80018b6: f5a3 73ca sub.w r3, r3, #404 ; 0x194
|
|
80018ba: 601a str r2, [r3, #0]
|
|
80018bc: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80018c0: f5a3 73cc sub.w r3, r3, #408 ; 0x198
|
|
80018c4: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
80018c8: 601a str r2, [r3, #0]
|
|
80018ca: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80018ce: f5a3 73cc sub.w r3, r3, #408 ; 0x198
|
|
80018d2: 681b ldr r3, [r3, #0]
|
|
80018d4: fa93 f2a3 rbit r2, r3
|
|
80018d8: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80018dc: f5a3 73ce sub.w r3, r3, #412 ; 0x19c
|
|
80018e0: 601a str r2, [r3, #0]
|
|
80018e2: 4b9c ldr r3, [pc, #624] ; (8001b54 <HAL_RCC_OscConfig+0xf78>)
|
|
80018e4: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80018e6: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
80018ea: f5a2 72d0 sub.w r2, r2, #416 ; 0x1a0
|
|
80018ee: f04f 7100 mov.w r1, #33554432 ; 0x2000000
|
|
80018f2: 6011 str r1, [r2, #0]
|
|
80018f4: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
80018f8: f5a2 72d0 sub.w r2, r2, #416 ; 0x1a0
|
|
80018fc: 6812 ldr r2, [r2, #0]
|
|
80018fe: fa92 f1a2 rbit r1, r2
|
|
8001902: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001906: f5a2 72d2 sub.w r2, r2, #420 ; 0x1a4
|
|
800190a: 6011 str r1, [r2, #0]
|
|
return result;
|
|
800190c: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001910: f5a2 72d2 sub.w r2, r2, #420 ; 0x1a4
|
|
8001914: 6812 ldr r2, [r2, #0]
|
|
8001916: fab2 f282 clz r2, r2
|
|
800191a: b2d2 uxtb r2, r2
|
|
800191c: f042 0220 orr.w r2, r2, #32
|
|
8001920: b2d2 uxtb r2, r2
|
|
8001922: f002 021f and.w r2, r2, #31
|
|
8001926: 2101 movs r1, #1
|
|
8001928: fa01 f202 lsl.w r2, r1, r2
|
|
800192c: 4013 ands r3, r2
|
|
800192e: 2b00 cmp r3, #0
|
|
8001930: d182 bne.n 8001838 <HAL_RCC_OscConfig+0xc5c>
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
RCC_OscInitStruct->PLL.PREDIV,
|
|
RCC_OscInitStruct->PLL.PLLMUL);
|
|
#else
|
|
/* Configure the main PLL clock source and multiplication factor. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
8001932: 4b88 ldr r3, [pc, #544] ; (8001b54 <HAL_RCC_OscConfig+0xf78>)
|
|
8001934: 685b ldr r3, [r3, #4]
|
|
8001936: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
|
|
800193a: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800193e: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8001942: 681b ldr r3, [r3, #0]
|
|
8001944: 6a59 ldr r1, [r3, #36] ; 0x24
|
|
8001946: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800194a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
800194e: 681b ldr r3, [r3, #0]
|
|
8001950: 6a1b ldr r3, [r3, #32]
|
|
8001952: 430b orrs r3, r1
|
|
8001954: 497f ldr r1, [pc, #508] ; (8001b54 <HAL_RCC_OscConfig+0xf78>)
|
|
8001956: 4313 orrs r3, r2
|
|
8001958: 604b str r3, [r1, #4]
|
|
800195a: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800195e: f5a3 73d4 sub.w r3, r3, #424 ; 0x1a8
|
|
8001962: f04f 7280 mov.w r2, #16777216 ; 0x1000000
|
|
8001966: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001968: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800196c: f5a3 73d4 sub.w r3, r3, #424 ; 0x1a8
|
|
8001970: 681b ldr r3, [r3, #0]
|
|
8001972: fa93 f2a3 rbit r2, r3
|
|
8001976: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
800197a: f5a3 73d6 sub.w r3, r3, #428 ; 0x1ac
|
|
800197e: 601a str r2, [r3, #0]
|
|
return result;
|
|
8001980: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001984: f5a3 73d6 sub.w r3, r3, #428 ; 0x1ac
|
|
8001988: 681b ldr r3, [r3, #0]
|
|
RCC_OscInitStruct->PLL.PLLMUL);
|
|
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
800198a: fab3 f383 clz r3, r3
|
|
800198e: b2db uxtb r3, r3
|
|
8001990: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
|
|
8001994: f503 1384 add.w r3, r3, #1081344 ; 0x108000
|
|
8001998: 009b lsls r3, r3, #2
|
|
800199a: 461a mov r2, r3
|
|
800199c: 2301 movs r3, #1
|
|
800199e: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80019a0: f7fe fe64 bl 800066c <HAL_GetTick>
|
|
80019a4: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
|
|
|
|
/* Wait till PLL is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
80019a8: e009 b.n 80019be <HAL_RCC_OscConfig+0xde2>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
80019aa: f7fe fe5f bl 800066c <HAL_GetTick>
|
|
80019ae: 4602 mov r2, r0
|
|
80019b0: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
|
|
80019b4: 1ad3 subs r3, r2, r3
|
|
80019b6: 2b02 cmp r3, #2
|
|
80019b8: d901 bls.n 80019be <HAL_RCC_OscConfig+0xde2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80019ba: 2303 movs r3, #3
|
|
80019bc: e144 b.n 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
80019be: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80019c2: f5a3 73d8 sub.w r3, r3, #432 ; 0x1b0
|
|
80019c6: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
80019ca: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80019cc: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80019d0: f5a3 73d8 sub.w r3, r3, #432 ; 0x1b0
|
|
80019d4: 681b ldr r3, [r3, #0]
|
|
80019d6: fa93 f2a3 rbit r2, r3
|
|
80019da: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80019de: f5a3 73da sub.w r3, r3, #436 ; 0x1b4
|
|
80019e2: 601a str r2, [r3, #0]
|
|
return result;
|
|
80019e4: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
80019e8: f5a3 73da sub.w r3, r3, #436 ; 0x1b4
|
|
80019ec: 681b ldr r3, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
80019ee: fab3 f383 clz r3, r3
|
|
80019f2: b2db uxtb r3, r3
|
|
80019f4: 095b lsrs r3, r3, #5
|
|
80019f6: b2db uxtb r3, r3
|
|
80019f8: f043 0301 orr.w r3, r3, #1
|
|
80019fc: b2db uxtb r3, r3
|
|
80019fe: 2b01 cmp r3, #1
|
|
8001a00: d102 bne.n 8001a08 <HAL_RCC_OscConfig+0xe2c>
|
|
8001a02: 4b54 ldr r3, [pc, #336] ; (8001b54 <HAL_RCC_OscConfig+0xf78>)
|
|
8001a04: 681b ldr r3, [r3, #0]
|
|
8001a06: e027 b.n 8001a58 <HAL_RCC_OscConfig+0xe7c>
|
|
8001a08: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001a0c: f5a3 73dc sub.w r3, r3, #440 ; 0x1b8
|
|
8001a10: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
8001a14: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001a16: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001a1a: f5a3 73dc sub.w r3, r3, #440 ; 0x1b8
|
|
8001a1e: 681b ldr r3, [r3, #0]
|
|
8001a20: fa93 f2a3 rbit r2, r3
|
|
8001a24: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001a28: f5a3 73de sub.w r3, r3, #444 ; 0x1bc
|
|
8001a2c: 601a str r2, [r3, #0]
|
|
8001a2e: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001a32: f5a3 73e0 sub.w r3, r3, #448 ; 0x1c0
|
|
8001a36: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
8001a3a: 601a str r2, [r3, #0]
|
|
8001a3c: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001a40: f5a3 73e0 sub.w r3, r3, #448 ; 0x1c0
|
|
8001a44: 681b ldr r3, [r3, #0]
|
|
8001a46: fa93 f2a3 rbit r2, r3
|
|
8001a4a: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001a4e: f5a3 73e2 sub.w r3, r3, #452 ; 0x1c4
|
|
8001a52: 601a str r2, [r3, #0]
|
|
8001a54: 4b3f ldr r3, [pc, #252] ; (8001b54 <HAL_RCC_OscConfig+0xf78>)
|
|
8001a56: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8001a58: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001a5c: f5a2 72e4 sub.w r2, r2, #456 ; 0x1c8
|
|
8001a60: f04f 7100 mov.w r1, #33554432 ; 0x2000000
|
|
8001a64: 6011 str r1, [r2, #0]
|
|
8001a66: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001a6a: f5a2 72e4 sub.w r2, r2, #456 ; 0x1c8
|
|
8001a6e: 6812 ldr r2, [r2, #0]
|
|
8001a70: fa92 f1a2 rbit r1, r2
|
|
8001a74: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001a78: f5a2 72e6 sub.w r2, r2, #460 ; 0x1cc
|
|
8001a7c: 6011 str r1, [r2, #0]
|
|
return result;
|
|
8001a7e: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001a82: f5a2 72e6 sub.w r2, r2, #460 ; 0x1cc
|
|
8001a86: 6812 ldr r2, [r2, #0]
|
|
8001a88: fab2 f282 clz r2, r2
|
|
8001a8c: b2d2 uxtb r2, r2
|
|
8001a8e: f042 0220 orr.w r2, r2, #32
|
|
8001a92: b2d2 uxtb r2, r2
|
|
8001a94: f002 021f and.w r2, r2, #31
|
|
8001a98: 2101 movs r1, #1
|
|
8001a9a: fa01 f202 lsl.w r2, r1, r2
|
|
8001a9e: 4013 ands r3, r2
|
|
8001aa0: 2b00 cmp r3, #0
|
|
8001aa2: d082 beq.n 80019aa <HAL_RCC_OscConfig+0xdce>
|
|
8001aa4: e0cf b.n 8001c46 <HAL_RCC_OscConfig+0x106a>
|
|
8001aa6: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001aaa: f5a3 73e8 sub.w r3, r3, #464 ; 0x1d0
|
|
8001aae: f04f 7280 mov.w r2, #16777216 ; 0x1000000
|
|
8001ab2: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001ab4: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001ab8: f5a3 73e8 sub.w r3, r3, #464 ; 0x1d0
|
|
8001abc: 681b ldr r3, [r3, #0]
|
|
8001abe: fa93 f2a3 rbit r2, r3
|
|
8001ac2: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001ac6: f5a3 73ea sub.w r3, r3, #468 ; 0x1d4
|
|
8001aca: 601a str r2, [r3, #0]
|
|
return result;
|
|
8001acc: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001ad0: f5a3 73ea sub.w r3, r3, #468 ; 0x1d4
|
|
8001ad4: 681b ldr r3, [r3, #0]
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8001ad6: fab3 f383 clz r3, r3
|
|
8001ada: b2db uxtb r3, r3
|
|
8001adc: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
|
|
8001ae0: f503 1384 add.w r3, r3, #1081344 ; 0x108000
|
|
8001ae4: 009b lsls r3, r3, #2
|
|
8001ae6: 461a mov r2, r3
|
|
8001ae8: 2300 movs r3, #0
|
|
8001aea: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001aec: f7fe fdbe bl 800066c <HAL_GetTick>
|
|
8001af0: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8001af4: e009 b.n 8001b0a <HAL_RCC_OscConfig+0xf2e>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
8001af6: f7fe fdb9 bl 800066c <HAL_GetTick>
|
|
8001afa: 4602 mov r2, r0
|
|
8001afc: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
|
|
8001b00: 1ad3 subs r3, r2, r3
|
|
8001b02: 2b02 cmp r3, #2
|
|
8001b04: d901 bls.n 8001b0a <HAL_RCC_OscConfig+0xf2e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8001b06: 2303 movs r3, #3
|
|
8001b08: e09e b.n 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
8001b0a: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001b0e: f5a3 73ec sub.w r3, r3, #472 ; 0x1d8
|
|
8001b12: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
8001b16: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001b18: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001b1c: f5a3 73ec sub.w r3, r3, #472 ; 0x1d8
|
|
8001b20: 681b ldr r3, [r3, #0]
|
|
8001b22: fa93 f2a3 rbit r2, r3
|
|
8001b26: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001b2a: f5a3 73ee sub.w r3, r3, #476 ; 0x1dc
|
|
8001b2e: 601a str r2, [r3, #0]
|
|
return result;
|
|
8001b30: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001b34: f5a3 73ee sub.w r3, r3, #476 ; 0x1dc
|
|
8001b38: 681b ldr r3, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8001b3a: fab3 f383 clz r3, r3
|
|
8001b3e: b2db uxtb r3, r3
|
|
8001b40: 095b lsrs r3, r3, #5
|
|
8001b42: b2db uxtb r3, r3
|
|
8001b44: f043 0301 orr.w r3, r3, #1
|
|
8001b48: b2db uxtb r3, r3
|
|
8001b4a: 2b01 cmp r3, #1
|
|
8001b4c: d104 bne.n 8001b58 <HAL_RCC_OscConfig+0xf7c>
|
|
8001b4e: 4b01 ldr r3, [pc, #4] ; (8001b54 <HAL_RCC_OscConfig+0xf78>)
|
|
8001b50: 681b ldr r3, [r3, #0]
|
|
8001b52: e029 b.n 8001ba8 <HAL_RCC_OscConfig+0xfcc>
|
|
8001b54: 40021000 .word 0x40021000
|
|
8001b58: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001b5c: f5a3 73f0 sub.w r3, r3, #480 ; 0x1e0
|
|
8001b60: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
8001b64: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001b66: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001b6a: f5a3 73f0 sub.w r3, r3, #480 ; 0x1e0
|
|
8001b6e: 681b ldr r3, [r3, #0]
|
|
8001b70: fa93 f2a3 rbit r2, r3
|
|
8001b74: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001b78: f5a3 73f2 sub.w r3, r3, #484 ; 0x1e4
|
|
8001b7c: 601a str r2, [r3, #0]
|
|
8001b7e: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001b82: f5a3 73f4 sub.w r3, r3, #488 ; 0x1e8
|
|
8001b86: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
8001b8a: 601a str r2, [r3, #0]
|
|
8001b8c: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001b90: f5a3 73f4 sub.w r3, r3, #488 ; 0x1e8
|
|
8001b94: 681b ldr r3, [r3, #0]
|
|
8001b96: fa93 f2a3 rbit r2, r3
|
|
8001b9a: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001b9e: f5a3 73f6 sub.w r3, r3, #492 ; 0x1ec
|
|
8001ba2: 601a str r2, [r3, #0]
|
|
8001ba4: 4b2b ldr r3, [pc, #172] ; (8001c54 <HAL_RCC_OscConfig+0x1078>)
|
|
8001ba6: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8001ba8: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001bac: f5a2 72f8 sub.w r2, r2, #496 ; 0x1f0
|
|
8001bb0: f04f 7100 mov.w r1, #33554432 ; 0x2000000
|
|
8001bb4: 6011 str r1, [r2, #0]
|
|
8001bb6: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001bba: f5a2 72f8 sub.w r2, r2, #496 ; 0x1f0
|
|
8001bbe: 6812 ldr r2, [r2, #0]
|
|
8001bc0: fa92 f1a2 rbit r1, r2
|
|
8001bc4: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001bc8: f5a2 72fa sub.w r2, r2, #500 ; 0x1f4
|
|
8001bcc: 6011 str r1, [r2, #0]
|
|
return result;
|
|
8001bce: f507 7200 add.w r2, r7, #512 ; 0x200
|
|
8001bd2: f5a2 72fa sub.w r2, r2, #500 ; 0x1f4
|
|
8001bd6: 6812 ldr r2, [r2, #0]
|
|
8001bd8: fab2 f282 clz r2, r2
|
|
8001bdc: b2d2 uxtb r2, r2
|
|
8001bde: f042 0220 orr.w r2, r2, #32
|
|
8001be2: b2d2 uxtb r2, r2
|
|
8001be4: f002 021f and.w r2, r2, #31
|
|
8001be8: 2101 movs r1, #1
|
|
8001bea: fa01 f202 lsl.w r2, r1, r2
|
|
8001bee: 4013 ands r3, r2
|
|
8001bf0: 2b00 cmp r3, #0
|
|
8001bf2: d180 bne.n 8001af6 <HAL_RCC_OscConfig+0xf1a>
|
|
8001bf4: e027 b.n 8001c46 <HAL_RCC_OscConfig+0x106a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8001bf6: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001bfa: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8001bfe: 681b ldr r3, [r3, #0]
|
|
8001c00: 69db ldr r3, [r3, #28]
|
|
8001c02: 2b01 cmp r3, #1
|
|
8001c04: d101 bne.n 8001c0a <HAL_RCC_OscConfig+0x102e>
|
|
{
|
|
return HAL_ERROR;
|
|
8001c06: 2301 movs r3, #1
|
|
8001c08: e01e b.n 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->CFGR;
|
|
8001c0a: 4b12 ldr r3, [pc, #72] ; (8001c54 <HAL_RCC_OscConfig+0x1078>)
|
|
8001c0c: 685b ldr r3, [r3, #4]
|
|
8001c0e: f8c7 31f4 str.w r3, [r7, #500] ; 0x1f4
|
|
pll_config2 = RCC->CFGR2;
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
|
|
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV))
|
|
#else
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8001c12: f8d7 31f4 ldr.w r3, [r7, #500] ; 0x1f4
|
|
8001c16: f403 3280 and.w r2, r3, #65536 ; 0x10000
|
|
8001c1a: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001c1e: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8001c22: 681b ldr r3, [r3, #0]
|
|
8001c24: 6a1b ldr r3, [r3, #32]
|
|
8001c26: 429a cmp r2, r3
|
|
8001c28: d10b bne.n 8001c42 <HAL_RCC_OscConfig+0x1066>
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
|
|
8001c2a: f8d7 31f4 ldr.w r3, [r7, #500] ; 0x1f4
|
|
8001c2e: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
|
|
8001c32: f507 7300 add.w r3, r7, #512 ; 0x200
|
|
8001c36: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
|
|
8001c3a: 681b ldr r3, [r3, #0]
|
|
8001c3c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8001c3e: 429a cmp r2, r3
|
|
8001c40: d001 beq.n 8001c46 <HAL_RCC_OscConfig+0x106a>
|
|
#endif
|
|
{
|
|
return HAL_ERROR;
|
|
8001c42: 2301 movs r3, #1
|
|
8001c44: e000 b.n 8001c48 <HAL_RCC_OscConfig+0x106c>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8001c46: 2300 movs r3, #0
|
|
}
|
|
8001c48: 4618 mov r0, r3
|
|
8001c4a: f507 7700 add.w r7, r7, #512 ; 0x200
|
|
8001c4e: 46bd mov sp, r7
|
|
8001c50: bd80 pop {r7, pc}
|
|
8001c52: bf00 nop
|
|
8001c54: 40021000 .word 0x40021000
|
|
|
|
08001c58 <HAL_RCC_ClockConfig>:
|
|
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
|
|
* currently used as system clock source.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8001c58: b580 push {r7, lr}
|
|
8001c5a: b09e sub sp, #120 ; 0x78
|
|
8001c5c: af00 add r7, sp, #0
|
|
8001c5e: 6078 str r0, [r7, #4]
|
|
8001c60: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart = 0U;
|
|
8001c62: 2300 movs r3, #0
|
|
8001c64: 677b str r3, [r7, #116] ; 0x74
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_ClkInitStruct == NULL)
|
|
8001c66: 687b ldr r3, [r7, #4]
|
|
8001c68: 2b00 cmp r3, #0
|
|
8001c6a: d101 bne.n 8001c70 <HAL_RCC_ClockConfig+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
8001c6c: 2301 movs r3, #1
|
|
8001c6e: e162 b.n 8001f36 <HAL_RCC_ClockConfig+0x2de>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if(FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8001c70: 4b90 ldr r3, [pc, #576] ; (8001eb4 <HAL_RCC_ClockConfig+0x25c>)
|
|
8001c72: 681b ldr r3, [r3, #0]
|
|
8001c74: f003 0307 and.w r3, r3, #7
|
|
8001c78: 683a ldr r2, [r7, #0]
|
|
8001c7a: 429a cmp r2, r3
|
|
8001c7c: d910 bls.n 8001ca0 <HAL_RCC_ClockConfig+0x48>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8001c7e: 4b8d ldr r3, [pc, #564] ; (8001eb4 <HAL_RCC_ClockConfig+0x25c>)
|
|
8001c80: 681b ldr r3, [r3, #0]
|
|
8001c82: f023 0207 bic.w r2, r3, #7
|
|
8001c86: 498b ldr r1, [pc, #556] ; (8001eb4 <HAL_RCC_ClockConfig+0x25c>)
|
|
8001c88: 683b ldr r3, [r7, #0]
|
|
8001c8a: 4313 orrs r3, r2
|
|
8001c8c: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8001c8e: 4b89 ldr r3, [pc, #548] ; (8001eb4 <HAL_RCC_ClockConfig+0x25c>)
|
|
8001c90: 681b ldr r3, [r3, #0]
|
|
8001c92: f003 0307 and.w r3, r3, #7
|
|
8001c96: 683a ldr r2, [r7, #0]
|
|
8001c98: 429a cmp r2, r3
|
|
8001c9a: d001 beq.n 8001ca0 <HAL_RCC_ClockConfig+0x48>
|
|
{
|
|
return HAL_ERROR;
|
|
8001c9c: 2301 movs r3, #1
|
|
8001c9e: e14a b.n 8001f36 <HAL_RCC_ClockConfig+0x2de>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8001ca0: 687b ldr r3, [r7, #4]
|
|
8001ca2: 681b ldr r3, [r3, #0]
|
|
8001ca4: f003 0302 and.w r3, r3, #2
|
|
8001ca8: 2b00 cmp r3, #0
|
|
8001caa: d008 beq.n 8001cbe <HAL_RCC_ClockConfig+0x66>
|
|
{
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8001cac: 4b82 ldr r3, [pc, #520] ; (8001eb8 <HAL_RCC_ClockConfig+0x260>)
|
|
8001cae: 685b ldr r3, [r3, #4]
|
|
8001cb0: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
8001cb4: 687b ldr r3, [r7, #4]
|
|
8001cb6: 689b ldr r3, [r3, #8]
|
|
8001cb8: 497f ldr r1, [pc, #508] ; (8001eb8 <HAL_RCC_ClockConfig+0x260>)
|
|
8001cba: 4313 orrs r3, r2
|
|
8001cbc: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8001cbe: 687b ldr r3, [r7, #4]
|
|
8001cc0: 681b ldr r3, [r3, #0]
|
|
8001cc2: f003 0301 and.w r3, r3, #1
|
|
8001cc6: 2b00 cmp r3, #0
|
|
8001cc8: f000 80dc beq.w 8001e84 <HAL_RCC_ClockConfig+0x22c>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8001ccc: 687b ldr r3, [r7, #4]
|
|
8001cce: 685b ldr r3, [r3, #4]
|
|
8001cd0: 2b01 cmp r3, #1
|
|
8001cd2: d13c bne.n 8001d4e <HAL_RCC_ClockConfig+0xf6>
|
|
8001cd4: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8001cd8: 673b str r3, [r7, #112] ; 0x70
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001cda: 6f3b ldr r3, [r7, #112] ; 0x70
|
|
8001cdc: fa93 f3a3 rbit r3, r3
|
|
8001ce0: 66fb str r3, [r7, #108] ; 0x6c
|
|
return result;
|
|
8001ce2: 6efb ldr r3, [r7, #108] ; 0x6c
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8001ce4: fab3 f383 clz r3, r3
|
|
8001ce8: b2db uxtb r3, r3
|
|
8001cea: 095b lsrs r3, r3, #5
|
|
8001cec: b2db uxtb r3, r3
|
|
8001cee: f043 0301 orr.w r3, r3, #1
|
|
8001cf2: b2db uxtb r3, r3
|
|
8001cf4: 2b01 cmp r3, #1
|
|
8001cf6: d102 bne.n 8001cfe <HAL_RCC_ClockConfig+0xa6>
|
|
8001cf8: 4b6f ldr r3, [pc, #444] ; (8001eb8 <HAL_RCC_ClockConfig+0x260>)
|
|
8001cfa: 681b ldr r3, [r3, #0]
|
|
8001cfc: e00f b.n 8001d1e <HAL_RCC_ClockConfig+0xc6>
|
|
8001cfe: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8001d02: 66bb str r3, [r7, #104] ; 0x68
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001d04: 6ebb ldr r3, [r7, #104] ; 0x68
|
|
8001d06: fa93 f3a3 rbit r3, r3
|
|
8001d0a: 667b str r3, [r7, #100] ; 0x64
|
|
8001d0c: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8001d10: 663b str r3, [r7, #96] ; 0x60
|
|
8001d12: 6e3b ldr r3, [r7, #96] ; 0x60
|
|
8001d14: fa93 f3a3 rbit r3, r3
|
|
8001d18: 65fb str r3, [r7, #92] ; 0x5c
|
|
8001d1a: 4b67 ldr r3, [pc, #412] ; (8001eb8 <HAL_RCC_ClockConfig+0x260>)
|
|
8001d1c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8001d1e: f44f 3200 mov.w r2, #131072 ; 0x20000
|
|
8001d22: 65ba str r2, [r7, #88] ; 0x58
|
|
8001d24: 6dba ldr r2, [r7, #88] ; 0x58
|
|
8001d26: fa92 f2a2 rbit r2, r2
|
|
8001d2a: 657a str r2, [r7, #84] ; 0x54
|
|
return result;
|
|
8001d2c: 6d7a ldr r2, [r7, #84] ; 0x54
|
|
8001d2e: fab2 f282 clz r2, r2
|
|
8001d32: b2d2 uxtb r2, r2
|
|
8001d34: f042 0220 orr.w r2, r2, #32
|
|
8001d38: b2d2 uxtb r2, r2
|
|
8001d3a: f002 021f and.w r2, r2, #31
|
|
8001d3e: 2101 movs r1, #1
|
|
8001d40: fa01 f202 lsl.w r2, r1, r2
|
|
8001d44: 4013 ands r3, r2
|
|
8001d46: 2b00 cmp r3, #0
|
|
8001d48: d17b bne.n 8001e42 <HAL_RCC_ClockConfig+0x1ea>
|
|
{
|
|
return HAL_ERROR;
|
|
8001d4a: 2301 movs r3, #1
|
|
8001d4c: e0f3 b.n 8001f36 <HAL_RCC_ClockConfig+0x2de>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
8001d4e: 687b ldr r3, [r7, #4]
|
|
8001d50: 685b ldr r3, [r3, #4]
|
|
8001d52: 2b02 cmp r3, #2
|
|
8001d54: d13c bne.n 8001dd0 <HAL_RCC_ClockConfig+0x178>
|
|
8001d56: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
8001d5a: 653b str r3, [r7, #80] ; 0x50
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001d5c: 6d3b ldr r3, [r7, #80] ; 0x50
|
|
8001d5e: fa93 f3a3 rbit r3, r3
|
|
8001d62: 64fb str r3, [r7, #76] ; 0x4c
|
|
return result;
|
|
8001d64: 6cfb ldr r3, [r7, #76] ; 0x4c
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8001d66: fab3 f383 clz r3, r3
|
|
8001d6a: b2db uxtb r3, r3
|
|
8001d6c: 095b lsrs r3, r3, #5
|
|
8001d6e: b2db uxtb r3, r3
|
|
8001d70: f043 0301 orr.w r3, r3, #1
|
|
8001d74: b2db uxtb r3, r3
|
|
8001d76: 2b01 cmp r3, #1
|
|
8001d78: d102 bne.n 8001d80 <HAL_RCC_ClockConfig+0x128>
|
|
8001d7a: 4b4f ldr r3, [pc, #316] ; (8001eb8 <HAL_RCC_ClockConfig+0x260>)
|
|
8001d7c: 681b ldr r3, [r3, #0]
|
|
8001d7e: e00f b.n 8001da0 <HAL_RCC_ClockConfig+0x148>
|
|
8001d80: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
8001d84: 64bb str r3, [r7, #72] ; 0x48
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001d86: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8001d88: fa93 f3a3 rbit r3, r3
|
|
8001d8c: 647b str r3, [r7, #68] ; 0x44
|
|
8001d8e: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
8001d92: 643b str r3, [r7, #64] ; 0x40
|
|
8001d94: 6c3b ldr r3, [r7, #64] ; 0x40
|
|
8001d96: fa93 f3a3 rbit r3, r3
|
|
8001d9a: 63fb str r3, [r7, #60] ; 0x3c
|
|
8001d9c: 4b46 ldr r3, [pc, #280] ; (8001eb8 <HAL_RCC_ClockConfig+0x260>)
|
|
8001d9e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8001da0: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
8001da4: 63ba str r2, [r7, #56] ; 0x38
|
|
8001da6: 6bba ldr r2, [r7, #56] ; 0x38
|
|
8001da8: fa92 f2a2 rbit r2, r2
|
|
8001dac: 637a str r2, [r7, #52] ; 0x34
|
|
return result;
|
|
8001dae: 6b7a ldr r2, [r7, #52] ; 0x34
|
|
8001db0: fab2 f282 clz r2, r2
|
|
8001db4: b2d2 uxtb r2, r2
|
|
8001db6: f042 0220 orr.w r2, r2, #32
|
|
8001dba: b2d2 uxtb r2, r2
|
|
8001dbc: f002 021f and.w r2, r2, #31
|
|
8001dc0: 2101 movs r1, #1
|
|
8001dc2: fa01 f202 lsl.w r2, r1, r2
|
|
8001dc6: 4013 ands r3, r2
|
|
8001dc8: 2b00 cmp r3, #0
|
|
8001dca: d13a bne.n 8001e42 <HAL_RCC_ClockConfig+0x1ea>
|
|
{
|
|
return HAL_ERROR;
|
|
8001dcc: 2301 movs r3, #1
|
|
8001dce: e0b2 b.n 8001f36 <HAL_RCC_ClockConfig+0x2de>
|
|
8001dd0: 2302 movs r3, #2
|
|
8001dd2: 633b str r3, [r7, #48] ; 0x30
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001dd4: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8001dd6: fa93 f3a3 rbit r3, r3
|
|
8001dda: 62fb str r3, [r7, #44] ; 0x2c
|
|
return result;
|
|
8001ddc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8001dde: fab3 f383 clz r3, r3
|
|
8001de2: b2db uxtb r3, r3
|
|
8001de4: 095b lsrs r3, r3, #5
|
|
8001de6: b2db uxtb r3, r3
|
|
8001de8: f043 0301 orr.w r3, r3, #1
|
|
8001dec: b2db uxtb r3, r3
|
|
8001dee: 2b01 cmp r3, #1
|
|
8001df0: d102 bne.n 8001df8 <HAL_RCC_ClockConfig+0x1a0>
|
|
8001df2: 4b31 ldr r3, [pc, #196] ; (8001eb8 <HAL_RCC_ClockConfig+0x260>)
|
|
8001df4: 681b ldr r3, [r3, #0]
|
|
8001df6: e00d b.n 8001e14 <HAL_RCC_ClockConfig+0x1bc>
|
|
8001df8: 2302 movs r3, #2
|
|
8001dfa: 62bb str r3, [r7, #40] ; 0x28
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001dfc: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8001dfe: fa93 f3a3 rbit r3, r3
|
|
8001e02: 627b str r3, [r7, #36] ; 0x24
|
|
8001e04: 2302 movs r3, #2
|
|
8001e06: 623b str r3, [r7, #32]
|
|
8001e08: 6a3b ldr r3, [r7, #32]
|
|
8001e0a: fa93 f3a3 rbit r3, r3
|
|
8001e0e: 61fb str r3, [r7, #28]
|
|
8001e10: 4b29 ldr r3, [pc, #164] ; (8001eb8 <HAL_RCC_ClockConfig+0x260>)
|
|
8001e12: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8001e14: 2202 movs r2, #2
|
|
8001e16: 61ba str r2, [r7, #24]
|
|
8001e18: 69ba ldr r2, [r7, #24]
|
|
8001e1a: fa92 f2a2 rbit r2, r2
|
|
8001e1e: 617a str r2, [r7, #20]
|
|
return result;
|
|
8001e20: 697a ldr r2, [r7, #20]
|
|
8001e22: fab2 f282 clz r2, r2
|
|
8001e26: b2d2 uxtb r2, r2
|
|
8001e28: f042 0220 orr.w r2, r2, #32
|
|
8001e2c: b2d2 uxtb r2, r2
|
|
8001e2e: f002 021f and.w r2, r2, #31
|
|
8001e32: 2101 movs r1, #1
|
|
8001e34: fa01 f202 lsl.w r2, r1, r2
|
|
8001e38: 4013 ands r3, r2
|
|
8001e3a: 2b00 cmp r3, #0
|
|
8001e3c: d101 bne.n 8001e42 <HAL_RCC_ClockConfig+0x1ea>
|
|
{
|
|
return HAL_ERROR;
|
|
8001e3e: 2301 movs r3, #1
|
|
8001e40: e079 b.n 8001f36 <HAL_RCC_ClockConfig+0x2de>
|
|
}
|
|
}
|
|
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
8001e42: 4b1d ldr r3, [pc, #116] ; (8001eb8 <HAL_RCC_ClockConfig+0x260>)
|
|
8001e44: 685b ldr r3, [r3, #4]
|
|
8001e46: f023 0203 bic.w r2, r3, #3
|
|
8001e4a: 687b ldr r3, [r7, #4]
|
|
8001e4c: 685b ldr r3, [r3, #4]
|
|
8001e4e: 491a ldr r1, [pc, #104] ; (8001eb8 <HAL_RCC_ClockConfig+0x260>)
|
|
8001e50: 4313 orrs r3, r2
|
|
8001e52: 604b str r3, [r1, #4]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001e54: f7fe fc0a bl 800066c <HAL_GetTick>
|
|
8001e58: 6778 str r0, [r7, #116] ; 0x74
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8001e5a: e00a b.n 8001e72 <HAL_RCC_ClockConfig+0x21a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8001e5c: f7fe fc06 bl 800066c <HAL_GetTick>
|
|
8001e60: 4602 mov r2, r0
|
|
8001e62: 6f7b ldr r3, [r7, #116] ; 0x74
|
|
8001e64: 1ad3 subs r3, r2, r3
|
|
8001e66: f241 3288 movw r2, #5000 ; 0x1388
|
|
8001e6a: 4293 cmp r3, r2
|
|
8001e6c: d901 bls.n 8001e72 <HAL_RCC_ClockConfig+0x21a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8001e6e: 2303 movs r3, #3
|
|
8001e70: e061 b.n 8001f36 <HAL_RCC_ClockConfig+0x2de>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8001e72: 4b11 ldr r3, [pc, #68] ; (8001eb8 <HAL_RCC_ClockConfig+0x260>)
|
|
8001e74: 685b ldr r3, [r3, #4]
|
|
8001e76: f003 020c and.w r2, r3, #12
|
|
8001e7a: 687b ldr r3, [r7, #4]
|
|
8001e7c: 685b ldr r3, [r3, #4]
|
|
8001e7e: 009b lsls r3, r3, #2
|
|
8001e80: 429a cmp r2, r3
|
|
8001e82: d1eb bne.n 8001e5c <HAL_RCC_ClockConfig+0x204>
|
|
}
|
|
}
|
|
}
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if(FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8001e84: 4b0b ldr r3, [pc, #44] ; (8001eb4 <HAL_RCC_ClockConfig+0x25c>)
|
|
8001e86: 681b ldr r3, [r3, #0]
|
|
8001e88: f003 0307 and.w r3, r3, #7
|
|
8001e8c: 683a ldr r2, [r7, #0]
|
|
8001e8e: 429a cmp r2, r3
|
|
8001e90: d214 bcs.n 8001ebc <HAL_RCC_ClockConfig+0x264>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8001e92: 4b08 ldr r3, [pc, #32] ; (8001eb4 <HAL_RCC_ClockConfig+0x25c>)
|
|
8001e94: 681b ldr r3, [r3, #0]
|
|
8001e96: f023 0207 bic.w r2, r3, #7
|
|
8001e9a: 4906 ldr r1, [pc, #24] ; (8001eb4 <HAL_RCC_ClockConfig+0x25c>)
|
|
8001e9c: 683b ldr r3, [r7, #0]
|
|
8001e9e: 4313 orrs r3, r2
|
|
8001ea0: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8001ea2: 4b04 ldr r3, [pc, #16] ; (8001eb4 <HAL_RCC_ClockConfig+0x25c>)
|
|
8001ea4: 681b ldr r3, [r3, #0]
|
|
8001ea6: f003 0307 and.w r3, r3, #7
|
|
8001eaa: 683a ldr r2, [r7, #0]
|
|
8001eac: 429a cmp r2, r3
|
|
8001eae: d005 beq.n 8001ebc <HAL_RCC_ClockConfig+0x264>
|
|
{
|
|
return HAL_ERROR;
|
|
8001eb0: 2301 movs r3, #1
|
|
8001eb2: e040 b.n 8001f36 <HAL_RCC_ClockConfig+0x2de>
|
|
8001eb4: 40022000 .word 0x40022000
|
|
8001eb8: 40021000 .word 0x40021000
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8001ebc: 687b ldr r3, [r7, #4]
|
|
8001ebe: 681b ldr r3, [r3, #0]
|
|
8001ec0: f003 0304 and.w r3, r3, #4
|
|
8001ec4: 2b00 cmp r3, #0
|
|
8001ec6: d008 beq.n 8001eda <HAL_RCC_ClockConfig+0x282>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8001ec8: 4b1d ldr r3, [pc, #116] ; (8001f40 <HAL_RCC_ClockConfig+0x2e8>)
|
|
8001eca: 685b ldr r3, [r3, #4]
|
|
8001ecc: f423 62e0 bic.w r2, r3, #1792 ; 0x700
|
|
8001ed0: 687b ldr r3, [r7, #4]
|
|
8001ed2: 68db ldr r3, [r3, #12]
|
|
8001ed4: 491a ldr r1, [pc, #104] ; (8001f40 <HAL_RCC_ClockConfig+0x2e8>)
|
|
8001ed6: 4313 orrs r3, r2
|
|
8001ed8: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8001eda: 687b ldr r3, [r7, #4]
|
|
8001edc: 681b ldr r3, [r3, #0]
|
|
8001ede: f003 0308 and.w r3, r3, #8
|
|
8001ee2: 2b00 cmp r3, #0
|
|
8001ee4: d009 beq.n 8001efa <HAL_RCC_ClockConfig+0x2a2>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
8001ee6: 4b16 ldr r3, [pc, #88] ; (8001f40 <HAL_RCC_ClockConfig+0x2e8>)
|
|
8001ee8: 685b ldr r3, [r3, #4]
|
|
8001eea: f423 5260 bic.w r2, r3, #14336 ; 0x3800
|
|
8001eee: 687b ldr r3, [r7, #4]
|
|
8001ef0: 691b ldr r3, [r3, #16]
|
|
8001ef2: 00db lsls r3, r3, #3
|
|
8001ef4: 4912 ldr r1, [pc, #72] ; (8001f40 <HAL_RCC_ClockConfig+0x2e8>)
|
|
8001ef6: 4313 orrs r3, r2
|
|
8001ef8: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
|
|
8001efa: f000 f829 bl 8001f50 <HAL_RCC_GetSysClockFreq>
|
|
8001efe: 4601 mov r1, r0
|
|
8001f00: 4b0f ldr r3, [pc, #60] ; (8001f40 <HAL_RCC_ClockConfig+0x2e8>)
|
|
8001f02: 685b ldr r3, [r3, #4]
|
|
8001f04: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
8001f08: 22f0 movs r2, #240 ; 0xf0
|
|
8001f0a: 613a str r2, [r7, #16]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8001f0c: 693a ldr r2, [r7, #16]
|
|
8001f0e: fa92 f2a2 rbit r2, r2
|
|
8001f12: 60fa str r2, [r7, #12]
|
|
return result;
|
|
8001f14: 68fa ldr r2, [r7, #12]
|
|
8001f16: fab2 f282 clz r2, r2
|
|
8001f1a: b2d2 uxtb r2, r2
|
|
8001f1c: 40d3 lsrs r3, r2
|
|
8001f1e: 4a09 ldr r2, [pc, #36] ; (8001f44 <HAL_RCC_ClockConfig+0x2ec>)
|
|
8001f20: 5cd3 ldrb r3, [r2, r3]
|
|
8001f22: fa21 f303 lsr.w r3, r1, r3
|
|
8001f26: 4a08 ldr r2, [pc, #32] ; (8001f48 <HAL_RCC_ClockConfig+0x2f0>)
|
|
8001f28: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
HAL_InitTick (uwTickPrio);
|
|
8001f2a: 4b08 ldr r3, [pc, #32] ; (8001f4c <HAL_RCC_ClockConfig+0x2f4>)
|
|
8001f2c: 681b ldr r3, [r3, #0]
|
|
8001f2e: 4618 mov r0, r3
|
|
8001f30: f7fe fb58 bl 80005e4 <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
8001f34: 2300 movs r3, #0
|
|
}
|
|
8001f36: 4618 mov r0, r3
|
|
8001f38: 3778 adds r7, #120 ; 0x78
|
|
8001f3a: 46bd mov sp, r7
|
|
8001f3c: bd80 pop {r7, pc}
|
|
8001f3e: bf00 nop
|
|
8001f40: 40021000 .word 0x40021000
|
|
8001f44: 08002c64 .word 0x08002c64
|
|
8001f48: 20000000 .word 0x20000000
|
|
8001f4c: 20000004 .word 0x20000004
|
|
|
|
08001f50 <HAL_RCC_GetSysClockFreq>:
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8001f50: b480 push {r7}
|
|
8001f52: b087 sub sp, #28
|
|
8001f54: af00 add r7, sp, #0
|
|
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
|
|
8001f56: 2300 movs r3, #0
|
|
8001f58: 60fb str r3, [r7, #12]
|
|
8001f5a: 2300 movs r3, #0
|
|
8001f5c: 60bb str r3, [r7, #8]
|
|
8001f5e: 2300 movs r3, #0
|
|
8001f60: 617b str r3, [r7, #20]
|
|
8001f62: 2300 movs r3, #0
|
|
8001f64: 607b str r3, [r7, #4]
|
|
uint32_t sysclockfreq = 0U;
|
|
8001f66: 2300 movs r3, #0
|
|
8001f68: 613b str r3, [r7, #16]
|
|
|
|
tmpreg = RCC->CFGR;
|
|
8001f6a: 4b1e ldr r3, [pc, #120] ; (8001fe4 <HAL_RCC_GetSysClockFreq+0x94>)
|
|
8001f6c: 685b ldr r3, [r3, #4]
|
|
8001f6e: 60fb str r3, [r7, #12]
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
|
8001f70: 68fb ldr r3, [r7, #12]
|
|
8001f72: f003 030c and.w r3, r3, #12
|
|
8001f76: 2b04 cmp r3, #4
|
|
8001f78: d002 beq.n 8001f80 <HAL_RCC_GetSysClockFreq+0x30>
|
|
8001f7a: 2b08 cmp r3, #8
|
|
8001f7c: d003 beq.n 8001f86 <HAL_RCC_GetSysClockFreq+0x36>
|
|
8001f7e: e026 b.n 8001fce <HAL_RCC_GetSysClockFreq+0x7e>
|
|
{
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8001f80: 4b19 ldr r3, [pc, #100] ; (8001fe8 <HAL_RCC_GetSysClockFreq+0x98>)
|
|
8001f82: 613b str r3, [r7, #16]
|
|
break;
|
|
8001f84: e026 b.n 8001fd4 <HAL_RCC_GetSysClockFreq+0x84>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
|
{
|
|
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
|
|
8001f86: 68fb ldr r3, [r7, #12]
|
|
8001f88: 0c9b lsrs r3, r3, #18
|
|
8001f8a: f003 030f and.w r3, r3, #15
|
|
8001f8e: 4a17 ldr r2, [pc, #92] ; (8001fec <HAL_RCC_GetSysClockFreq+0x9c>)
|
|
8001f90: 5cd3 ldrb r3, [r2, r3]
|
|
8001f92: 607b str r3, [r7, #4]
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_Pos];
|
|
8001f94: 4b13 ldr r3, [pc, #76] ; (8001fe4 <HAL_RCC_GetSysClockFreq+0x94>)
|
|
8001f96: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8001f98: f003 030f and.w r3, r3, #15
|
|
8001f9c: 4a14 ldr r2, [pc, #80] ; (8001ff0 <HAL_RCC_GetSysClockFreq+0xa0>)
|
|
8001f9e: 5cd3 ldrb r3, [r2, r3]
|
|
8001fa0: 60bb str r3, [r7, #8]
|
|
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
|
|
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
|
|
8001fa2: 68fb ldr r3, [r7, #12]
|
|
8001fa4: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8001fa8: 2b00 cmp r3, #0
|
|
8001faa: d008 beq.n 8001fbe <HAL_RCC_GetSysClockFreq+0x6e>
|
|
{
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
|
|
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
|
|
8001fac: 4a0e ldr r2, [pc, #56] ; (8001fe8 <HAL_RCC_GetSysClockFreq+0x98>)
|
|
8001fae: 68bb ldr r3, [r7, #8]
|
|
8001fb0: fbb2 f2f3 udiv r2, r2, r3
|
|
8001fb4: 687b ldr r3, [r7, #4]
|
|
8001fb6: fb02 f303 mul.w r3, r2, r3
|
|
8001fba: 617b str r3, [r7, #20]
|
|
8001fbc: e004 b.n 8001fc8 <HAL_RCC_GetSysClockFreq+0x78>
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
|
|
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
|
|
8001fbe: 687b ldr r3, [r7, #4]
|
|
8001fc0: 4a0c ldr r2, [pc, #48] ; (8001ff4 <HAL_RCC_GetSysClockFreq+0xa4>)
|
|
8001fc2: fb02 f303 mul.w r3, r2, r3
|
|
8001fc6: 617b str r3, [r7, #20]
|
|
{
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
|
|
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
|
|
}
|
|
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
|
|
sysclockfreq = pllclk;
|
|
8001fc8: 697b ldr r3, [r7, #20]
|
|
8001fca: 613b str r3, [r7, #16]
|
|
break;
|
|
8001fcc: e002 b.n 8001fd4 <HAL_RCC_GetSysClockFreq+0x84>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
default: /* HSI used as system clock */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8001fce: 4b06 ldr r3, [pc, #24] ; (8001fe8 <HAL_RCC_GetSysClockFreq+0x98>)
|
|
8001fd0: 613b str r3, [r7, #16]
|
|
break;
|
|
8001fd2: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8001fd4: 693b ldr r3, [r7, #16]
|
|
}
|
|
8001fd6: 4618 mov r0, r3
|
|
8001fd8: 371c adds r7, #28
|
|
8001fda: 46bd mov sp, r7
|
|
8001fdc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001fe0: 4770 bx lr
|
|
8001fe2: bf00 nop
|
|
8001fe4: 40021000 .word 0x40021000
|
|
8001fe8: 007a1200 .word 0x007a1200
|
|
8001fec: 08002c74 .word 0x08002c74
|
|
8001ff0: 08002c84 .word 0x08002c84
|
|
8001ff4: 003d0900 .word 0x003d0900
|
|
|
|
08001ff8 <HAL_TIM_PWM_Init>:
|
|
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
|
|
* @param htim TIM PWM handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
8001ff8: b580 push {r7, lr}
|
|
8001ffa: b082 sub sp, #8
|
|
8001ffc: af00 add r7, sp, #0
|
|
8001ffe: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
8002000: 687b ldr r3, [r7, #4]
|
|
8002002: 2b00 cmp r3, #0
|
|
8002004: d101 bne.n 800200a <HAL_TIM_PWM_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8002006: 2301 movs r3, #1
|
|
8002008: e049 b.n 800209e <HAL_TIM_PWM_Init+0xa6>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
800200a: 687b ldr r3, [r7, #4]
|
|
800200c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
8002010: b2db uxtb r3, r3
|
|
8002012: 2b00 cmp r3, #0
|
|
8002014: d106 bne.n 8002024 <HAL_TIM_PWM_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8002016: 687b ldr r3, [r7, #4]
|
|
8002018: 2200 movs r2, #0
|
|
800201a: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->PWM_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_PWM_MspInit(htim);
|
|
800201e: 6878 ldr r0, [r7, #4]
|
|
8002020: f7fe fa12 bl 8000448 <HAL_TIM_PWM_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8002024: 687b ldr r3, [r7, #4]
|
|
8002026: 2202 movs r2, #2
|
|
8002028: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Init the base time for the PWM */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
800202c: 687b ldr r3, [r7, #4]
|
|
800202e: 681a ldr r2, [r3, #0]
|
|
8002030: 687b ldr r3, [r7, #4]
|
|
8002032: 3304 adds r3, #4
|
|
8002034: 4619 mov r1, r3
|
|
8002036: 4610 mov r0, r2
|
|
8002038: f000 fa30 bl 800249c <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
800203c: 687b ldr r3, [r7, #4]
|
|
800203e: 2201 movs r2, #1
|
|
8002040: f883 2048 strb.w r2, [r3, #72] ; 0x48
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8002044: 687b ldr r3, [r7, #4]
|
|
8002046: 2201 movs r2, #1
|
|
8002048: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
800204c: 687b ldr r3, [r7, #4]
|
|
800204e: 2201 movs r2, #1
|
|
8002050: f883 203f strb.w r2, [r3, #63] ; 0x3f
|
|
8002054: 687b ldr r3, [r7, #4]
|
|
8002056: 2201 movs r2, #1
|
|
8002058: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
800205c: 687b ldr r3, [r7, #4]
|
|
800205e: 2201 movs r2, #1
|
|
8002060: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
8002064: 687b ldr r3, [r7, #4]
|
|
8002066: 2201 movs r2, #1
|
|
8002068: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
800206c: 687b ldr r3, [r7, #4]
|
|
800206e: 2201 movs r2, #1
|
|
8002070: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8002074: 687b ldr r3, [r7, #4]
|
|
8002076: 2201 movs r2, #1
|
|
8002078: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
800207c: 687b ldr r3, [r7, #4]
|
|
800207e: 2201 movs r2, #1
|
|
8002080: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
8002084: 687b ldr r3, [r7, #4]
|
|
8002086: 2201 movs r2, #1
|
|
8002088: f883 2046 strb.w r2, [r3, #70] ; 0x46
|
|
800208c: 687b ldr r3, [r7, #4]
|
|
800208e: 2201 movs r2, #1
|
|
8002090: f883 2047 strb.w r2, [r3, #71] ; 0x47
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8002094: 687b ldr r3, [r7, #4]
|
|
8002096: 2201 movs r2, #1
|
|
8002098: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
return HAL_OK;
|
|
800209c: 2300 movs r3, #0
|
|
}
|
|
800209e: 4618 mov r0, r3
|
|
80020a0: 3708 adds r7, #8
|
|
80020a2: 46bd mov sp, r7
|
|
80020a4: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080020a8 <HAL_TIM_PWM_Start>:
|
|
* @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
|
|
* (*) Value not defined for all devices
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
80020a8: b580 push {r7, lr}
|
|
80020aa: b084 sub sp, #16
|
|
80020ac: af00 add r7, sp, #0
|
|
80020ae: 6078 str r0, [r7, #4]
|
|
80020b0: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
|
/* Check the TIM channel state */
|
|
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
|
80020b2: 683b ldr r3, [r7, #0]
|
|
80020b4: 2b00 cmp r3, #0
|
|
80020b6: d109 bne.n 80020cc <HAL_TIM_PWM_Start+0x24>
|
|
80020b8: 687b ldr r3, [r7, #4]
|
|
80020ba: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
|
|
80020be: b2db uxtb r3, r3
|
|
80020c0: 2b01 cmp r3, #1
|
|
80020c2: bf14 ite ne
|
|
80020c4: 2301 movne r3, #1
|
|
80020c6: 2300 moveq r3, #0
|
|
80020c8: b2db uxtb r3, r3
|
|
80020ca: e03c b.n 8002146 <HAL_TIM_PWM_Start+0x9e>
|
|
80020cc: 683b ldr r3, [r7, #0]
|
|
80020ce: 2b04 cmp r3, #4
|
|
80020d0: d109 bne.n 80020e6 <HAL_TIM_PWM_Start+0x3e>
|
|
80020d2: 687b ldr r3, [r7, #4]
|
|
80020d4: f893 303f ldrb.w r3, [r3, #63] ; 0x3f
|
|
80020d8: b2db uxtb r3, r3
|
|
80020da: 2b01 cmp r3, #1
|
|
80020dc: bf14 ite ne
|
|
80020de: 2301 movne r3, #1
|
|
80020e0: 2300 moveq r3, #0
|
|
80020e2: b2db uxtb r3, r3
|
|
80020e4: e02f b.n 8002146 <HAL_TIM_PWM_Start+0x9e>
|
|
80020e6: 683b ldr r3, [r7, #0]
|
|
80020e8: 2b08 cmp r3, #8
|
|
80020ea: d109 bne.n 8002100 <HAL_TIM_PWM_Start+0x58>
|
|
80020ec: 687b ldr r3, [r7, #4]
|
|
80020ee: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
|
|
80020f2: b2db uxtb r3, r3
|
|
80020f4: 2b01 cmp r3, #1
|
|
80020f6: bf14 ite ne
|
|
80020f8: 2301 movne r3, #1
|
|
80020fa: 2300 moveq r3, #0
|
|
80020fc: b2db uxtb r3, r3
|
|
80020fe: e022 b.n 8002146 <HAL_TIM_PWM_Start+0x9e>
|
|
8002100: 683b ldr r3, [r7, #0]
|
|
8002102: 2b0c cmp r3, #12
|
|
8002104: d109 bne.n 800211a <HAL_TIM_PWM_Start+0x72>
|
|
8002106: 687b ldr r3, [r7, #4]
|
|
8002108: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
|
|
800210c: b2db uxtb r3, r3
|
|
800210e: 2b01 cmp r3, #1
|
|
8002110: bf14 ite ne
|
|
8002112: 2301 movne r3, #1
|
|
8002114: 2300 moveq r3, #0
|
|
8002116: b2db uxtb r3, r3
|
|
8002118: e015 b.n 8002146 <HAL_TIM_PWM_Start+0x9e>
|
|
800211a: 683b ldr r3, [r7, #0]
|
|
800211c: 2b10 cmp r3, #16
|
|
800211e: d109 bne.n 8002134 <HAL_TIM_PWM_Start+0x8c>
|
|
8002120: 687b ldr r3, [r7, #4]
|
|
8002122: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
|
|
8002126: b2db uxtb r3, r3
|
|
8002128: 2b01 cmp r3, #1
|
|
800212a: bf14 ite ne
|
|
800212c: 2301 movne r3, #1
|
|
800212e: 2300 moveq r3, #0
|
|
8002130: b2db uxtb r3, r3
|
|
8002132: e008 b.n 8002146 <HAL_TIM_PWM_Start+0x9e>
|
|
8002134: 687b ldr r3, [r7, #4]
|
|
8002136: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
|
|
800213a: b2db uxtb r3, r3
|
|
800213c: 2b01 cmp r3, #1
|
|
800213e: bf14 ite ne
|
|
8002140: 2301 movne r3, #1
|
|
8002142: 2300 moveq r3, #0
|
|
8002144: b2db uxtb r3, r3
|
|
8002146: 2b00 cmp r3, #0
|
|
8002148: d001 beq.n 800214e <HAL_TIM_PWM_Start+0xa6>
|
|
{
|
|
return HAL_ERROR;
|
|
800214a: 2301 movs r3, #1
|
|
800214c: e083 b.n 8002256 <HAL_TIM_PWM_Start+0x1ae>
|
|
}
|
|
|
|
/* Set the TIM channel state */
|
|
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
800214e: 683b ldr r3, [r7, #0]
|
|
8002150: 2b00 cmp r3, #0
|
|
8002152: d104 bne.n 800215e <HAL_TIM_PWM_Start+0xb6>
|
|
8002154: 687b ldr r3, [r7, #4]
|
|
8002156: 2202 movs r2, #2
|
|
8002158: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
800215c: e023 b.n 80021a6 <HAL_TIM_PWM_Start+0xfe>
|
|
800215e: 683b ldr r3, [r7, #0]
|
|
8002160: 2b04 cmp r3, #4
|
|
8002162: d104 bne.n 800216e <HAL_TIM_PWM_Start+0xc6>
|
|
8002164: 687b ldr r3, [r7, #4]
|
|
8002166: 2202 movs r2, #2
|
|
8002168: f883 203f strb.w r2, [r3, #63] ; 0x3f
|
|
800216c: e01b b.n 80021a6 <HAL_TIM_PWM_Start+0xfe>
|
|
800216e: 683b ldr r3, [r7, #0]
|
|
8002170: 2b08 cmp r3, #8
|
|
8002172: d104 bne.n 800217e <HAL_TIM_PWM_Start+0xd6>
|
|
8002174: 687b ldr r3, [r7, #4]
|
|
8002176: 2202 movs r2, #2
|
|
8002178: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
800217c: e013 b.n 80021a6 <HAL_TIM_PWM_Start+0xfe>
|
|
800217e: 683b ldr r3, [r7, #0]
|
|
8002180: 2b0c cmp r3, #12
|
|
8002182: d104 bne.n 800218e <HAL_TIM_PWM_Start+0xe6>
|
|
8002184: 687b ldr r3, [r7, #4]
|
|
8002186: 2202 movs r2, #2
|
|
8002188: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
800218c: e00b b.n 80021a6 <HAL_TIM_PWM_Start+0xfe>
|
|
800218e: 683b ldr r3, [r7, #0]
|
|
8002190: 2b10 cmp r3, #16
|
|
8002192: d104 bne.n 800219e <HAL_TIM_PWM_Start+0xf6>
|
|
8002194: 687b ldr r3, [r7, #4]
|
|
8002196: 2202 movs r2, #2
|
|
8002198: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
800219c: e003 b.n 80021a6 <HAL_TIM_PWM_Start+0xfe>
|
|
800219e: 687b ldr r3, [r7, #4]
|
|
80021a0: 2202 movs r2, #2
|
|
80021a2: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
|
|
/* Enable the Capture compare channel */
|
|
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
80021a6: 687b ldr r3, [r7, #4]
|
|
80021a8: 681b ldr r3, [r3, #0]
|
|
80021aa: 2201 movs r2, #1
|
|
80021ac: 6839 ldr r1, [r7, #0]
|
|
80021ae: 4618 mov r0, r3
|
|
80021b0: f000 fc94 bl 8002adc <TIM_CCxChannelCmd>
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
80021b4: 687b ldr r3, [r7, #4]
|
|
80021b6: 681b ldr r3, [r3, #0]
|
|
80021b8: 4a29 ldr r2, [pc, #164] ; (8002260 <HAL_TIM_PWM_Start+0x1b8>)
|
|
80021ba: 4293 cmp r3, r2
|
|
80021bc: d00e beq.n 80021dc <HAL_TIM_PWM_Start+0x134>
|
|
80021be: 687b ldr r3, [r7, #4]
|
|
80021c0: 681b ldr r3, [r3, #0]
|
|
80021c2: 4a28 ldr r2, [pc, #160] ; (8002264 <HAL_TIM_PWM_Start+0x1bc>)
|
|
80021c4: 4293 cmp r3, r2
|
|
80021c6: d009 beq.n 80021dc <HAL_TIM_PWM_Start+0x134>
|
|
80021c8: 687b ldr r3, [r7, #4]
|
|
80021ca: 681b ldr r3, [r3, #0]
|
|
80021cc: 4a26 ldr r2, [pc, #152] ; (8002268 <HAL_TIM_PWM_Start+0x1c0>)
|
|
80021ce: 4293 cmp r3, r2
|
|
80021d0: d004 beq.n 80021dc <HAL_TIM_PWM_Start+0x134>
|
|
80021d2: 687b ldr r3, [r7, #4]
|
|
80021d4: 681b ldr r3, [r3, #0]
|
|
80021d6: 4a25 ldr r2, [pc, #148] ; (800226c <HAL_TIM_PWM_Start+0x1c4>)
|
|
80021d8: 4293 cmp r3, r2
|
|
80021da: d101 bne.n 80021e0 <HAL_TIM_PWM_Start+0x138>
|
|
80021dc: 2301 movs r3, #1
|
|
80021de: e000 b.n 80021e2 <HAL_TIM_PWM_Start+0x13a>
|
|
80021e0: 2300 movs r3, #0
|
|
80021e2: 2b00 cmp r3, #0
|
|
80021e4: d007 beq.n 80021f6 <HAL_TIM_PWM_Start+0x14e>
|
|
{
|
|
/* Enable the main output */
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
80021e6: 687b ldr r3, [r7, #4]
|
|
80021e8: 681b ldr r3, [r3, #0]
|
|
80021ea: 6c5a ldr r2, [r3, #68] ; 0x44
|
|
80021ec: 687b ldr r3, [r7, #4]
|
|
80021ee: 681b ldr r3, [r3, #0]
|
|
80021f0: f442 4200 orr.w r2, r2, #32768 ; 0x8000
|
|
80021f4: 645a str r2, [r3, #68] ; 0x44
|
|
}
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
80021f6: 687b ldr r3, [r7, #4]
|
|
80021f8: 681b ldr r3, [r3, #0]
|
|
80021fa: 4a19 ldr r2, [pc, #100] ; (8002260 <HAL_TIM_PWM_Start+0x1b8>)
|
|
80021fc: 4293 cmp r3, r2
|
|
80021fe: d009 beq.n 8002214 <HAL_TIM_PWM_Start+0x16c>
|
|
8002200: 687b ldr r3, [r7, #4]
|
|
8002202: 681b ldr r3, [r3, #0]
|
|
8002204: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
8002208: d004 beq.n 8002214 <HAL_TIM_PWM_Start+0x16c>
|
|
800220a: 687b ldr r3, [r7, #4]
|
|
800220c: 681b ldr r3, [r3, #0]
|
|
800220e: 4a15 ldr r2, [pc, #84] ; (8002264 <HAL_TIM_PWM_Start+0x1bc>)
|
|
8002210: 4293 cmp r3, r2
|
|
8002212: d115 bne.n 8002240 <HAL_TIM_PWM_Start+0x198>
|
|
{
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
8002214: 687b ldr r3, [r7, #4]
|
|
8002216: 681b ldr r3, [r3, #0]
|
|
8002218: 689a ldr r2, [r3, #8]
|
|
800221a: 4b15 ldr r3, [pc, #84] ; (8002270 <HAL_TIM_PWM_Start+0x1c8>)
|
|
800221c: 4013 ands r3, r2
|
|
800221e: 60fb str r3, [r7, #12]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8002220: 68fb ldr r3, [r7, #12]
|
|
8002222: 2b06 cmp r3, #6
|
|
8002224: d015 beq.n 8002252 <HAL_TIM_PWM_Start+0x1aa>
|
|
8002226: 68fb ldr r3, [r7, #12]
|
|
8002228: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
800222c: d011 beq.n 8002252 <HAL_TIM_PWM_Start+0x1aa>
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
800222e: 687b ldr r3, [r7, #4]
|
|
8002230: 681b ldr r3, [r3, #0]
|
|
8002232: 681a ldr r2, [r3, #0]
|
|
8002234: 687b ldr r3, [r7, #4]
|
|
8002236: 681b ldr r3, [r3, #0]
|
|
8002238: f042 0201 orr.w r2, r2, #1
|
|
800223c: 601a str r2, [r3, #0]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
800223e: e008 b.n 8002252 <HAL_TIM_PWM_Start+0x1aa>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
8002240: 687b ldr r3, [r7, #4]
|
|
8002242: 681b ldr r3, [r3, #0]
|
|
8002244: 681a ldr r2, [r3, #0]
|
|
8002246: 687b ldr r3, [r7, #4]
|
|
8002248: 681b ldr r3, [r3, #0]
|
|
800224a: f042 0201 orr.w r2, r2, #1
|
|
800224e: 601a str r2, [r3, #0]
|
|
8002250: e000 b.n 8002254 <HAL_TIM_PWM_Start+0x1ac>
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8002252: bf00 nop
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8002254: 2300 movs r3, #0
|
|
}
|
|
8002256: 4618 mov r0, r3
|
|
8002258: 3710 adds r7, #16
|
|
800225a: 46bd mov sp, r7
|
|
800225c: bd80 pop {r7, pc}
|
|
800225e: bf00 nop
|
|
8002260: 40012c00 .word 0x40012c00
|
|
8002264: 40014000 .word 0x40014000
|
|
8002268: 40014400 .word 0x40014400
|
|
800226c: 40014800 .word 0x40014800
|
|
8002270: 00010007 .word 0x00010007
|
|
|
|
08002274 <HAL_TIM_PWM_ConfigChannel>:
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
const TIM_OC_InitTypeDef *sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
8002274: b580 push {r7, lr}
|
|
8002276: b086 sub sp, #24
|
|
8002278: af00 add r7, sp, #0
|
|
800227a: 60f8 str r0, [r7, #12]
|
|
800227c: 60b9 str r1, [r7, #8]
|
|
800227e: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8002280: 2300 movs r3, #0
|
|
8002282: 75fb strb r3, [r7, #23]
|
|
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
8002284: 68fb ldr r3, [r7, #12]
|
|
8002286: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
800228a: 2b01 cmp r3, #1
|
|
800228c: d101 bne.n 8002292 <HAL_TIM_PWM_ConfigChannel+0x1e>
|
|
800228e: 2302 movs r3, #2
|
|
8002290: e0ff b.n 8002492 <HAL_TIM_PWM_ConfigChannel+0x21e>
|
|
8002292: 68fb ldr r3, [r7, #12]
|
|
8002294: 2201 movs r2, #1
|
|
8002296: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
switch (Channel)
|
|
800229a: 687b ldr r3, [r7, #4]
|
|
800229c: 2b14 cmp r3, #20
|
|
800229e: f200 80f0 bhi.w 8002482 <HAL_TIM_PWM_ConfigChannel+0x20e>
|
|
80022a2: a201 add r2, pc, #4 ; (adr r2, 80022a8 <HAL_TIM_PWM_ConfigChannel+0x34>)
|
|
80022a4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80022a8: 080022fd .word 0x080022fd
|
|
80022ac: 08002483 .word 0x08002483
|
|
80022b0: 08002483 .word 0x08002483
|
|
80022b4: 08002483 .word 0x08002483
|
|
80022b8: 0800233d .word 0x0800233d
|
|
80022bc: 08002483 .word 0x08002483
|
|
80022c0: 08002483 .word 0x08002483
|
|
80022c4: 08002483 .word 0x08002483
|
|
80022c8: 0800237f .word 0x0800237f
|
|
80022cc: 08002483 .word 0x08002483
|
|
80022d0: 08002483 .word 0x08002483
|
|
80022d4: 08002483 .word 0x08002483
|
|
80022d8: 080023bf .word 0x080023bf
|
|
80022dc: 08002483 .word 0x08002483
|
|
80022e0: 08002483 .word 0x08002483
|
|
80022e4: 08002483 .word 0x08002483
|
|
80022e8: 08002401 .word 0x08002401
|
|
80022ec: 08002483 .word 0x08002483
|
|
80022f0: 08002483 .word 0x08002483
|
|
80022f4: 08002483 .word 0x08002483
|
|
80022f8: 08002441 .word 0x08002441
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 1 in PWM mode */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
80022fc: 68fb ldr r3, [r7, #12]
|
|
80022fe: 681b ldr r3, [r3, #0]
|
|
8002300: 68b9 ldr r1, [r7, #8]
|
|
8002302: 4618 mov r0, r3
|
|
8002304: f000 f944 bl 8002590 <TIM_OC1_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel1 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
|
8002308: 68fb ldr r3, [r7, #12]
|
|
800230a: 681b ldr r3, [r3, #0]
|
|
800230c: 699a ldr r2, [r3, #24]
|
|
800230e: 68fb ldr r3, [r7, #12]
|
|
8002310: 681b ldr r3, [r3, #0]
|
|
8002312: f042 0208 orr.w r2, r2, #8
|
|
8002316: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
|
8002318: 68fb ldr r3, [r7, #12]
|
|
800231a: 681b ldr r3, [r3, #0]
|
|
800231c: 699a ldr r2, [r3, #24]
|
|
800231e: 68fb ldr r3, [r7, #12]
|
|
8002320: 681b ldr r3, [r3, #0]
|
|
8002322: f022 0204 bic.w r2, r2, #4
|
|
8002326: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode;
|
|
8002328: 68fb ldr r3, [r7, #12]
|
|
800232a: 681b ldr r3, [r3, #0]
|
|
800232c: 6999 ldr r1, [r3, #24]
|
|
800232e: 68bb ldr r3, [r7, #8]
|
|
8002330: 691a ldr r2, [r3, #16]
|
|
8002332: 68fb ldr r3, [r7, #12]
|
|
8002334: 681b ldr r3, [r3, #0]
|
|
8002336: 430a orrs r2, r1
|
|
8002338: 619a str r2, [r3, #24]
|
|
break;
|
|
800233a: e0a5 b.n 8002488 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 2 in PWM mode */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
800233c: 68fb ldr r3, [r7, #12]
|
|
800233e: 681b ldr r3, [r3, #0]
|
|
8002340: 68b9 ldr r1, [r7, #8]
|
|
8002342: 4618 mov r0, r3
|
|
8002344: f000 f9aa bl 800269c <TIM_OC2_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel2 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
|
|
8002348: 68fb ldr r3, [r7, #12]
|
|
800234a: 681b ldr r3, [r3, #0]
|
|
800234c: 699a ldr r2, [r3, #24]
|
|
800234e: 68fb ldr r3, [r7, #12]
|
|
8002350: 681b ldr r3, [r3, #0]
|
|
8002352: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
8002356: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
|
|
8002358: 68fb ldr r3, [r7, #12]
|
|
800235a: 681b ldr r3, [r3, #0]
|
|
800235c: 699a ldr r2, [r3, #24]
|
|
800235e: 68fb ldr r3, [r7, #12]
|
|
8002360: 681b ldr r3, [r3, #0]
|
|
8002362: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
8002366: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
|
|
8002368: 68fb ldr r3, [r7, #12]
|
|
800236a: 681b ldr r3, [r3, #0]
|
|
800236c: 6999 ldr r1, [r3, #24]
|
|
800236e: 68bb ldr r3, [r7, #8]
|
|
8002370: 691b ldr r3, [r3, #16]
|
|
8002372: 021a lsls r2, r3, #8
|
|
8002374: 68fb ldr r3, [r7, #12]
|
|
8002376: 681b ldr r3, [r3, #0]
|
|
8002378: 430a orrs r2, r1
|
|
800237a: 619a str r2, [r3, #24]
|
|
break;
|
|
800237c: e084 b.n 8002488 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 3 in PWM mode */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
800237e: 68fb ldr r3, [r7, #12]
|
|
8002380: 681b ldr r3, [r3, #0]
|
|
8002382: 68b9 ldr r1, [r7, #8]
|
|
8002384: 4618 mov r0, r3
|
|
8002386: f000 fa09 bl 800279c <TIM_OC3_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel3 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
|
|
800238a: 68fb ldr r3, [r7, #12]
|
|
800238c: 681b ldr r3, [r3, #0]
|
|
800238e: 69da ldr r2, [r3, #28]
|
|
8002390: 68fb ldr r3, [r7, #12]
|
|
8002392: 681b ldr r3, [r3, #0]
|
|
8002394: f042 0208 orr.w r2, r2, #8
|
|
8002398: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
|
800239a: 68fb ldr r3, [r7, #12]
|
|
800239c: 681b ldr r3, [r3, #0]
|
|
800239e: 69da ldr r2, [r3, #28]
|
|
80023a0: 68fb ldr r3, [r7, #12]
|
|
80023a2: 681b ldr r3, [r3, #0]
|
|
80023a4: f022 0204 bic.w r2, r2, #4
|
|
80023a8: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode;
|
|
80023aa: 68fb ldr r3, [r7, #12]
|
|
80023ac: 681b ldr r3, [r3, #0]
|
|
80023ae: 69d9 ldr r1, [r3, #28]
|
|
80023b0: 68bb ldr r3, [r7, #8]
|
|
80023b2: 691a ldr r2, [r3, #16]
|
|
80023b4: 68fb ldr r3, [r7, #12]
|
|
80023b6: 681b ldr r3, [r3, #0]
|
|
80023b8: 430a orrs r2, r1
|
|
80023ba: 61da str r2, [r3, #28]
|
|
break;
|
|
80023bc: e064 b.n 8002488 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 4 in PWM mode */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
80023be: 68fb ldr r3, [r7, #12]
|
|
80023c0: 681b ldr r3, [r3, #0]
|
|
80023c2: 68b9 ldr r1, [r7, #8]
|
|
80023c4: 4618 mov r0, r3
|
|
80023c6: f000 fa67 bl 8002898 <TIM_OC4_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel4 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
|
|
80023ca: 68fb ldr r3, [r7, #12]
|
|
80023cc: 681b ldr r3, [r3, #0]
|
|
80023ce: 69da ldr r2, [r3, #28]
|
|
80023d0: 68fb ldr r3, [r7, #12]
|
|
80023d2: 681b ldr r3, [r3, #0]
|
|
80023d4: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
80023d8: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
|
|
80023da: 68fb ldr r3, [r7, #12]
|
|
80023dc: 681b ldr r3, [r3, #0]
|
|
80023de: 69da ldr r2, [r3, #28]
|
|
80023e0: 68fb ldr r3, [r7, #12]
|
|
80023e2: 681b ldr r3, [r3, #0]
|
|
80023e4: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
80023e8: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
|
|
80023ea: 68fb ldr r3, [r7, #12]
|
|
80023ec: 681b ldr r3, [r3, #0]
|
|
80023ee: 69d9 ldr r1, [r3, #28]
|
|
80023f0: 68bb ldr r3, [r7, #8]
|
|
80023f2: 691b ldr r3, [r3, #16]
|
|
80023f4: 021a lsls r2, r3, #8
|
|
80023f6: 68fb ldr r3, [r7, #12]
|
|
80023f8: 681b ldr r3, [r3, #0]
|
|
80023fa: 430a orrs r2, r1
|
|
80023fc: 61da str r2, [r3, #28]
|
|
break;
|
|
80023fe: e043 b.n 8002488 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 5 in PWM mode */
|
|
TIM_OC5_SetConfig(htim->Instance, sConfig);
|
|
8002400: 68fb ldr r3, [r7, #12]
|
|
8002402: 681b ldr r3, [r3, #0]
|
|
8002404: 68b9 ldr r1, [r7, #8]
|
|
8002406: 4618 mov r0, r3
|
|
8002408: f000 faaa bl 8002960 <TIM_OC5_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel5*/
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
|
|
800240c: 68fb ldr r3, [r7, #12]
|
|
800240e: 681b ldr r3, [r3, #0]
|
|
8002410: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
8002412: 68fb ldr r3, [r7, #12]
|
|
8002414: 681b ldr r3, [r3, #0]
|
|
8002416: f042 0208 orr.w r2, r2, #8
|
|
800241a: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
|
|
800241c: 68fb ldr r3, [r7, #12]
|
|
800241e: 681b ldr r3, [r3, #0]
|
|
8002420: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
8002422: 68fb ldr r3, [r7, #12]
|
|
8002424: 681b ldr r3, [r3, #0]
|
|
8002426: f022 0204 bic.w r2, r2, #4
|
|
800242a: 655a str r2, [r3, #84] ; 0x54
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode;
|
|
800242c: 68fb ldr r3, [r7, #12]
|
|
800242e: 681b ldr r3, [r3, #0]
|
|
8002430: 6d59 ldr r1, [r3, #84] ; 0x54
|
|
8002432: 68bb ldr r3, [r7, #8]
|
|
8002434: 691a ldr r2, [r3, #16]
|
|
8002436: 68fb ldr r3, [r7, #12]
|
|
8002438: 681b ldr r3, [r3, #0]
|
|
800243a: 430a orrs r2, r1
|
|
800243c: 655a str r2, [r3, #84] ; 0x54
|
|
break;
|
|
800243e: e023 b.n 8002488 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 6 in PWM mode */
|
|
TIM_OC6_SetConfig(htim->Instance, sConfig);
|
|
8002440: 68fb ldr r3, [r7, #12]
|
|
8002442: 681b ldr r3, [r3, #0]
|
|
8002444: 68b9 ldr r1, [r7, #8]
|
|
8002446: 4618 mov r0, r3
|
|
8002448: f000 fae8 bl 8002a1c <TIM_OC6_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel6 */
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
|
|
800244c: 68fb ldr r3, [r7, #12]
|
|
800244e: 681b ldr r3, [r3, #0]
|
|
8002450: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
8002452: 68fb ldr r3, [r7, #12]
|
|
8002454: 681b ldr r3, [r3, #0]
|
|
8002456: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
800245a: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
|
|
800245c: 68fb ldr r3, [r7, #12]
|
|
800245e: 681b ldr r3, [r3, #0]
|
|
8002460: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
8002462: 68fb ldr r3, [r7, #12]
|
|
8002464: 681b ldr r3, [r3, #0]
|
|
8002466: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
800246a: 655a str r2, [r3, #84] ; 0x54
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
|
|
800246c: 68fb ldr r3, [r7, #12]
|
|
800246e: 681b ldr r3, [r3, #0]
|
|
8002470: 6d59 ldr r1, [r3, #84] ; 0x54
|
|
8002472: 68bb ldr r3, [r7, #8]
|
|
8002474: 691b ldr r3, [r3, #16]
|
|
8002476: 021a lsls r2, r3, #8
|
|
8002478: 68fb ldr r3, [r7, #12]
|
|
800247a: 681b ldr r3, [r3, #0]
|
|
800247c: 430a orrs r2, r1
|
|
800247e: 655a str r2, [r3, #84] ; 0x54
|
|
break;
|
|
8002480: e002 b.n 8002488 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
}
|
|
#endif /* TIM_CCER_CC6E */
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
8002482: 2301 movs r3, #1
|
|
8002484: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8002486: bf00 nop
|
|
}
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8002488: 68fb ldr r3, [r7, #12]
|
|
800248a: 2200 movs r2, #0
|
|
800248c: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return status;
|
|
8002490: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8002492: 4618 mov r0, r3
|
|
8002494: 3718 adds r7, #24
|
|
8002496: 46bd mov sp, r7
|
|
8002498: bd80 pop {r7, pc}
|
|
800249a: bf00 nop
|
|
|
|
0800249c <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
800249c: b480 push {r7}
|
|
800249e: b085 sub sp, #20
|
|
80024a0: af00 add r7, sp, #0
|
|
80024a2: 6078 str r0, [r7, #4]
|
|
80024a4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
80024a6: 687b ldr r3, [r7, #4]
|
|
80024a8: 681b ldr r3, [r3, #0]
|
|
80024aa: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
80024ac: 687b ldr r3, [r7, #4]
|
|
80024ae: 4a34 ldr r2, [pc, #208] ; (8002580 <TIM_Base_SetConfig+0xe4>)
|
|
80024b0: 4293 cmp r3, r2
|
|
80024b2: d003 beq.n 80024bc <TIM_Base_SetConfig+0x20>
|
|
80024b4: 687b ldr r3, [r7, #4]
|
|
80024b6: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
80024ba: d108 bne.n 80024ce <TIM_Base_SetConfig+0x32>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
80024bc: 68fb ldr r3, [r7, #12]
|
|
80024be: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
80024c2: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
80024c4: 683b ldr r3, [r7, #0]
|
|
80024c6: 685b ldr r3, [r3, #4]
|
|
80024c8: 68fa ldr r2, [r7, #12]
|
|
80024ca: 4313 orrs r3, r2
|
|
80024cc: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
80024ce: 687b ldr r3, [r7, #4]
|
|
80024d0: 4a2b ldr r2, [pc, #172] ; (8002580 <TIM_Base_SetConfig+0xe4>)
|
|
80024d2: 4293 cmp r3, r2
|
|
80024d4: d00f beq.n 80024f6 <TIM_Base_SetConfig+0x5a>
|
|
80024d6: 687b ldr r3, [r7, #4]
|
|
80024d8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
80024dc: d00b beq.n 80024f6 <TIM_Base_SetConfig+0x5a>
|
|
80024de: 687b ldr r3, [r7, #4]
|
|
80024e0: 4a28 ldr r2, [pc, #160] ; (8002584 <TIM_Base_SetConfig+0xe8>)
|
|
80024e2: 4293 cmp r3, r2
|
|
80024e4: d007 beq.n 80024f6 <TIM_Base_SetConfig+0x5a>
|
|
80024e6: 687b ldr r3, [r7, #4]
|
|
80024e8: 4a27 ldr r2, [pc, #156] ; (8002588 <TIM_Base_SetConfig+0xec>)
|
|
80024ea: 4293 cmp r3, r2
|
|
80024ec: d003 beq.n 80024f6 <TIM_Base_SetConfig+0x5a>
|
|
80024ee: 687b ldr r3, [r7, #4]
|
|
80024f0: 4a26 ldr r2, [pc, #152] ; (800258c <TIM_Base_SetConfig+0xf0>)
|
|
80024f2: 4293 cmp r3, r2
|
|
80024f4: d108 bne.n 8002508 <TIM_Base_SetConfig+0x6c>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
80024f6: 68fb ldr r3, [r7, #12]
|
|
80024f8: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
80024fc: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
80024fe: 683b ldr r3, [r7, #0]
|
|
8002500: 68db ldr r3, [r3, #12]
|
|
8002502: 68fa ldr r2, [r7, #12]
|
|
8002504: 4313 orrs r3, r2
|
|
8002506: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
8002508: 68fb ldr r3, [r7, #12]
|
|
800250a: f023 0280 bic.w r2, r3, #128 ; 0x80
|
|
800250e: 683b ldr r3, [r7, #0]
|
|
8002510: 695b ldr r3, [r3, #20]
|
|
8002512: 4313 orrs r3, r2
|
|
8002514: 60fb str r3, [r7, #12]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
8002516: 687b ldr r3, [r7, #4]
|
|
8002518: 68fa ldr r2, [r7, #12]
|
|
800251a: 601a str r2, [r3, #0]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
800251c: 683b ldr r3, [r7, #0]
|
|
800251e: 689a ldr r2, [r3, #8]
|
|
8002520: 687b ldr r3, [r7, #4]
|
|
8002522: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
8002524: 683b ldr r3, [r7, #0]
|
|
8002526: 681a ldr r2, [r3, #0]
|
|
8002528: 687b ldr r3, [r7, #4]
|
|
800252a: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
800252c: 687b ldr r3, [r7, #4]
|
|
800252e: 4a14 ldr r2, [pc, #80] ; (8002580 <TIM_Base_SetConfig+0xe4>)
|
|
8002530: 4293 cmp r3, r2
|
|
8002532: d00b beq.n 800254c <TIM_Base_SetConfig+0xb0>
|
|
8002534: 687b ldr r3, [r7, #4]
|
|
8002536: 4a13 ldr r2, [pc, #76] ; (8002584 <TIM_Base_SetConfig+0xe8>)
|
|
8002538: 4293 cmp r3, r2
|
|
800253a: d007 beq.n 800254c <TIM_Base_SetConfig+0xb0>
|
|
800253c: 687b ldr r3, [r7, #4]
|
|
800253e: 4a12 ldr r2, [pc, #72] ; (8002588 <TIM_Base_SetConfig+0xec>)
|
|
8002540: 4293 cmp r3, r2
|
|
8002542: d003 beq.n 800254c <TIM_Base_SetConfig+0xb0>
|
|
8002544: 687b ldr r3, [r7, #4]
|
|
8002546: 4a11 ldr r2, [pc, #68] ; (800258c <TIM_Base_SetConfig+0xf0>)
|
|
8002548: 4293 cmp r3, r2
|
|
800254a: d103 bne.n 8002554 <TIM_Base_SetConfig+0xb8>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
800254c: 683b ldr r3, [r7, #0]
|
|
800254e: 691a ldr r2, [r3, #16]
|
|
8002550: 687b ldr r3, [r7, #4]
|
|
8002552: 631a str r2, [r3, #48] ; 0x30
|
|
}
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
8002554: 687b ldr r3, [r7, #4]
|
|
8002556: 2201 movs r2, #1
|
|
8002558: 615a str r2, [r3, #20]
|
|
|
|
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
|
|
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
|
|
800255a: 687b ldr r3, [r7, #4]
|
|
800255c: 691b ldr r3, [r3, #16]
|
|
800255e: f003 0301 and.w r3, r3, #1
|
|
8002562: 2b01 cmp r3, #1
|
|
8002564: d105 bne.n 8002572 <TIM_Base_SetConfig+0xd6>
|
|
{
|
|
/* Clear the update flag */
|
|
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
|
|
8002566: 687b ldr r3, [r7, #4]
|
|
8002568: 691b ldr r3, [r3, #16]
|
|
800256a: f023 0201 bic.w r2, r3, #1
|
|
800256e: 687b ldr r3, [r7, #4]
|
|
8002570: 611a str r2, [r3, #16]
|
|
}
|
|
}
|
|
8002572: bf00 nop
|
|
8002574: 3714 adds r7, #20
|
|
8002576: 46bd mov sp, r7
|
|
8002578: f85d 7b04 ldr.w r7, [sp], #4
|
|
800257c: 4770 bx lr
|
|
800257e: bf00 nop
|
|
8002580: 40012c00 .word 0x40012c00
|
|
8002584: 40014000 .word 0x40014000
|
|
8002588: 40014400 .word 0x40014400
|
|
800258c: 40014800 .word 0x40014800
|
|
|
|
08002590 <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
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|
{
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8002590: b480 push {r7}
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|
8002592: b087 sub sp, #28
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|
8002594: af00 add r7, sp, #0
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|
8002596: 6078 str r0, [r7, #4]
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|
8002598: 6039 str r1, [r7, #0]
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|
uint32_t tmpccmrx;
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|
uint32_t tmpccer;
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|
uint32_t tmpcr2;
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|
|
|
/* Get the TIMx CCER register value */
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|
tmpccer = TIMx->CCER;
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|
800259a: 687b ldr r3, [r7, #4]
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|
800259c: 6a1b ldr r3, [r3, #32]
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|
800259e: 617b str r3, [r7, #20]
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|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
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|
TIMx->CCER &= ~TIM_CCER_CC1E;
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|
80025a0: 687b ldr r3, [r7, #4]
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|
80025a2: 6a1b ldr r3, [r3, #32]
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|
80025a4: f023 0201 bic.w r2, r3, #1
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|
80025a8: 687b ldr r3, [r7, #4]
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|
80025aa: 621a str r2, [r3, #32]
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|
|
|
/* Get the TIMx CR2 register value */
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tmpcr2 = TIMx->CR2;
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|
80025ac: 687b ldr r3, [r7, #4]
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80025ae: 685b ldr r3, [r3, #4]
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80025b0: 613b str r3, [r7, #16]
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|
|
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = TIMx->CCMR1;
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80025b2: 687b ldr r3, [r7, #4]
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80025b4: 699b ldr r3, [r3, #24]
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80025b6: 60fb str r3, [r7, #12]
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|
|
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= ~TIM_CCMR1_OC1M;
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80025b8: 68fb ldr r3, [r7, #12]
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|
80025ba: f423 3380 bic.w r3, r3, #65536 ; 0x10000
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80025be: f023 0370 bic.w r3, r3, #112 ; 0x70
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80025c2: 60fb str r3, [r7, #12]
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tmpccmrx &= ~TIM_CCMR1_CC1S;
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80025c4: 68fb ldr r3, [r7, #12]
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80025c6: f023 0303 bic.w r3, r3, #3
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|
80025ca: 60fb str r3, [r7, #12]
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/* Select the Output Compare Mode */
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tmpccmrx |= OC_Config->OCMode;
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80025cc: 683b ldr r3, [r7, #0]
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|
80025ce: 681b ldr r3, [r3, #0]
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|
80025d0: 68fa ldr r2, [r7, #12]
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|
80025d2: 4313 orrs r3, r2
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80025d4: 60fb str r3, [r7, #12]
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|
|
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/* Reset the Output Polarity level */
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tmpccer &= ~TIM_CCER_CC1P;
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80025d6: 697b ldr r3, [r7, #20]
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80025d8: f023 0302 bic.w r3, r3, #2
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80025dc: 617b str r3, [r7, #20]
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/* Set the Output Compare Polarity */
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tmpccer |= OC_Config->OCPolarity;
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80025de: 683b ldr r3, [r7, #0]
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|
80025e0: 689b ldr r3, [r3, #8]
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|
80025e2: 697a ldr r2, [r7, #20]
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|
80025e4: 4313 orrs r3, r2
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80025e6: 617b str r3, [r7, #20]
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|
|
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if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
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80025e8: 687b ldr r3, [r7, #4]
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80025ea: 4a28 ldr r2, [pc, #160] ; (800268c <TIM_OC1_SetConfig+0xfc>)
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80025ec: 4293 cmp r3, r2
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80025ee: d00b beq.n 8002608 <TIM_OC1_SetConfig+0x78>
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80025f0: 687b ldr r3, [r7, #4]
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80025f2: 4a27 ldr r2, [pc, #156] ; (8002690 <TIM_OC1_SetConfig+0x100>)
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80025f4: 4293 cmp r3, r2
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80025f6: d007 beq.n 8002608 <TIM_OC1_SetConfig+0x78>
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80025f8: 687b ldr r3, [r7, #4]
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80025fa: 4a26 ldr r2, [pc, #152] ; (8002694 <TIM_OC1_SetConfig+0x104>)
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80025fc: 4293 cmp r3, r2
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80025fe: d003 beq.n 8002608 <TIM_OC1_SetConfig+0x78>
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8002600: 687b ldr r3, [r7, #4]
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8002602: 4a25 ldr r2, [pc, #148] ; (8002698 <TIM_OC1_SetConfig+0x108>)
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8002604: 4293 cmp r3, r2
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8002606: d10c bne.n 8002622 <TIM_OC1_SetConfig+0x92>
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{
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/* Check parameters */
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assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
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|
|
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/* Reset the Output N Polarity level */
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tmpccer &= ~TIM_CCER_CC1NP;
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8002608: 697b ldr r3, [r7, #20]
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800260a: f023 0308 bic.w r3, r3, #8
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800260e: 617b str r3, [r7, #20]
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/* Set the Output N Polarity */
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tmpccer |= OC_Config->OCNPolarity;
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8002610: 683b ldr r3, [r7, #0]
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8002612: 68db ldr r3, [r3, #12]
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8002614: 697a ldr r2, [r7, #20]
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|
8002616: 4313 orrs r3, r2
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|
8002618: 617b str r3, [r7, #20]
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|
/* Reset the Output N State */
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|
tmpccer &= ~TIM_CCER_CC1NE;
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|
800261a: 697b ldr r3, [r7, #20]
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|
800261c: f023 0304 bic.w r3, r3, #4
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|
8002620: 617b str r3, [r7, #20]
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|
}
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|
|
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if (IS_TIM_BREAK_INSTANCE(TIMx))
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8002622: 687b ldr r3, [r7, #4]
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8002624: 4a19 ldr r2, [pc, #100] ; (800268c <TIM_OC1_SetConfig+0xfc>)
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8002626: 4293 cmp r3, r2
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8002628: d00b beq.n 8002642 <TIM_OC1_SetConfig+0xb2>
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800262a: 687b ldr r3, [r7, #4]
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800262c: 4a18 ldr r2, [pc, #96] ; (8002690 <TIM_OC1_SetConfig+0x100>)
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800262e: 4293 cmp r3, r2
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8002630: d007 beq.n 8002642 <TIM_OC1_SetConfig+0xb2>
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8002632: 687b ldr r3, [r7, #4]
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8002634: 4a17 ldr r2, [pc, #92] ; (8002694 <TIM_OC1_SetConfig+0x104>)
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8002636: 4293 cmp r3, r2
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8002638: d003 beq.n 8002642 <TIM_OC1_SetConfig+0xb2>
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800263a: 687b ldr r3, [r7, #4]
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800263c: 4a16 ldr r2, [pc, #88] ; (8002698 <TIM_OC1_SetConfig+0x108>)
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800263e: 4293 cmp r3, r2
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8002640: d111 bne.n 8002666 <TIM_OC1_SetConfig+0xd6>
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/* Check parameters */
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assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
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assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
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|
|
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/* Reset the Output Compare and Output Compare N IDLE State */
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tmpcr2 &= ~TIM_CR2_OIS1;
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8002642: 693b ldr r3, [r7, #16]
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8002644: f423 7380 bic.w r3, r3, #256 ; 0x100
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8002648: 613b str r3, [r7, #16]
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tmpcr2 &= ~TIM_CR2_OIS1N;
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800264a: 693b ldr r3, [r7, #16]
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800264c: f423 7300 bic.w r3, r3, #512 ; 0x200
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8002650: 613b str r3, [r7, #16]
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/* Set the Output Idle state */
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tmpcr2 |= OC_Config->OCIdleState;
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8002652: 683b ldr r3, [r7, #0]
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8002654: 695b ldr r3, [r3, #20]
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8002656: 693a ldr r2, [r7, #16]
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8002658: 4313 orrs r3, r2
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800265a: 613b str r3, [r7, #16]
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/* Set the Output N Idle state */
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tmpcr2 |= OC_Config->OCNIdleState;
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800265c: 683b ldr r3, [r7, #0]
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800265e: 699b ldr r3, [r3, #24]
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8002660: 693a ldr r2, [r7, #16]
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8002662: 4313 orrs r3, r2
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8002664: 613b str r3, [r7, #16]
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}
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/* Write to TIMx CR2 */
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TIMx->CR2 = tmpcr2;
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8002666: 687b ldr r3, [r7, #4]
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8002668: 693a ldr r2, [r7, #16]
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800266a: 605a str r2, [r3, #4]
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/* Write to TIMx CCMR1 */
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TIMx->CCMR1 = tmpccmrx;
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800266c: 687b ldr r3, [r7, #4]
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800266e: 68fa ldr r2, [r7, #12]
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8002670: 619a str r2, [r3, #24]
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/* Set the Capture Compare Register value */
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TIMx->CCR1 = OC_Config->Pulse;
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8002672: 683b ldr r3, [r7, #0]
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8002674: 685a ldr r2, [r3, #4]
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8002676: 687b ldr r3, [r7, #4]
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8002678: 635a str r2, [r3, #52] ; 0x34
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/* Write to TIMx CCER */
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TIMx->CCER = tmpccer;
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800267a: 687b ldr r3, [r7, #4]
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800267c: 697a ldr r2, [r7, #20]
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800267e: 621a str r2, [r3, #32]
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}
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8002680: bf00 nop
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8002682: 371c adds r7, #28
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8002684: 46bd mov sp, r7
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8002686: f85d 7b04 ldr.w r7, [sp], #4
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800268a: 4770 bx lr
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800268c: 40012c00 .word 0x40012c00
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8002690: 40014000 .word 0x40014000
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8002694: 40014400 .word 0x40014400
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8002698: 40014800 .word 0x40014800
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0800269c <TIM_OC2_SetConfig>:
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* @param TIMx to select the TIM peripheral
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* @param OC_Config The output configuration structure
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* @retval None
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*/
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void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
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{
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800269c: b480 push {r7}
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800269e: b087 sub sp, #28
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80026a0: af00 add r7, sp, #0
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80026a2: 6078 str r0, [r7, #4]
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80026a4: 6039 str r1, [r7, #0]
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uint32_t tmpccmrx;
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uint32_t tmpccer;
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uint32_t tmpcr2;
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/* Get the TIMx CCER register value */
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tmpccer = TIMx->CCER;
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80026a6: 687b ldr r3, [r7, #4]
|
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80026a8: 6a1b ldr r3, [r3, #32]
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80026aa: 617b str r3, [r7, #20]
|
|
|
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/* Disable the Channel 2: Reset the CC2E Bit */
|
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TIMx->CCER &= ~TIM_CCER_CC2E;
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80026ac: 687b ldr r3, [r7, #4]
|
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80026ae: 6a1b ldr r3, [r3, #32]
|
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80026b0: f023 0210 bic.w r2, r3, #16
|
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80026b4: 687b ldr r3, [r7, #4]
|
|
80026b6: 621a str r2, [r3, #32]
|
|
|
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/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80026b8: 687b ldr r3, [r7, #4]
|
|
80026ba: 685b ldr r3, [r3, #4]
|
|
80026bc: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
80026be: 687b ldr r3, [r7, #4]
|
|
80026c0: 699b ldr r3, [r3, #24]
|
|
80026c2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
80026c4: 68fb ldr r3, [r7, #12]
|
|
80026c6: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
|
|
80026ca: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
|
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80026ce: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
80026d0: 68fb ldr r3, [r7, #12]
|
|
80026d2: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
80026d6: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
80026d8: 683b ldr r3, [r7, #0]
|
|
80026da: 681b ldr r3, [r3, #0]
|
|
80026dc: 021b lsls r3, r3, #8
|
|
80026de: 68fa ldr r2, [r7, #12]
|
|
80026e0: 4313 orrs r3, r2
|
|
80026e2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
80026e4: 697b ldr r3, [r7, #20]
|
|
80026e6: f023 0320 bic.w r3, r3, #32
|
|
80026ea: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
80026ec: 683b ldr r3, [r7, #0]
|
|
80026ee: 689b ldr r3, [r3, #8]
|
|
80026f0: 011b lsls r3, r3, #4
|
|
80026f2: 697a ldr r2, [r7, #20]
|
|
80026f4: 4313 orrs r3, r2
|
|
80026f6: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
80026f8: 687b ldr r3, [r7, #4]
|
|
80026fa: 4a24 ldr r2, [pc, #144] ; (800278c <TIM_OC2_SetConfig+0xf0>)
|
|
80026fc: 4293 cmp r3, r2
|
|
80026fe: d10d bne.n 800271c <TIM_OC2_SetConfig+0x80>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
8002700: 697b ldr r3, [r7, #20]
|
|
8002702: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
8002706: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
8002708: 683b ldr r3, [r7, #0]
|
|
800270a: 68db ldr r3, [r3, #12]
|
|
800270c: 011b lsls r3, r3, #4
|
|
800270e: 697a ldr r2, [r7, #20]
|
|
8002710: 4313 orrs r3, r2
|
|
8002712: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
8002714: 697b ldr r3, [r7, #20]
|
|
8002716: f023 0340 bic.w r3, r3, #64 ; 0x40
|
|
800271a: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800271c: 687b ldr r3, [r7, #4]
|
|
800271e: 4a1b ldr r2, [pc, #108] ; (800278c <TIM_OC2_SetConfig+0xf0>)
|
|
8002720: 4293 cmp r3, r2
|
|
8002722: d00b beq.n 800273c <TIM_OC2_SetConfig+0xa0>
|
|
8002724: 687b ldr r3, [r7, #4]
|
|
8002726: 4a1a ldr r2, [pc, #104] ; (8002790 <TIM_OC2_SetConfig+0xf4>)
|
|
8002728: 4293 cmp r3, r2
|
|
800272a: d007 beq.n 800273c <TIM_OC2_SetConfig+0xa0>
|
|
800272c: 687b ldr r3, [r7, #4]
|
|
800272e: 4a19 ldr r2, [pc, #100] ; (8002794 <TIM_OC2_SetConfig+0xf8>)
|
|
8002730: 4293 cmp r3, r2
|
|
8002732: d003 beq.n 800273c <TIM_OC2_SetConfig+0xa0>
|
|
8002734: 687b ldr r3, [r7, #4]
|
|
8002736: 4a18 ldr r2, [pc, #96] ; (8002798 <TIM_OC2_SetConfig+0xfc>)
|
|
8002738: 4293 cmp r3, r2
|
|
800273a: d113 bne.n 8002764 <TIM_OC2_SetConfig+0xc8>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
800273c: 693b ldr r3, [r7, #16]
|
|
800273e: f423 6380 bic.w r3, r3, #1024 ; 0x400
|
|
8002742: 613b str r3, [r7, #16]
|
|
#if defined(TIM_CR2_OIS2N)
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
8002744: 693b ldr r3, [r7, #16]
|
|
8002746: f423 6300 bic.w r3, r3, #2048 ; 0x800
|
|
800274a: 613b str r3, [r7, #16]
|
|
#endif /* TIM_CR2_OIS2N */
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
800274c: 683b ldr r3, [r7, #0]
|
|
800274e: 695b ldr r3, [r3, #20]
|
|
8002750: 009b lsls r3, r3, #2
|
|
8002752: 693a ldr r2, [r7, #16]
|
|
8002754: 4313 orrs r3, r2
|
|
8002756: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
8002758: 683b ldr r3, [r7, #0]
|
|
800275a: 699b ldr r3, [r3, #24]
|
|
800275c: 009b lsls r3, r3, #2
|
|
800275e: 693a ldr r2, [r7, #16]
|
|
8002760: 4313 orrs r3, r2
|
|
8002762: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8002764: 687b ldr r3, [r7, #4]
|
|
8002766: 693a ldr r2, [r7, #16]
|
|
8002768: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
800276a: 687b ldr r3, [r7, #4]
|
|
800276c: 68fa ldr r2, [r7, #12]
|
|
800276e: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
8002770: 683b ldr r3, [r7, #0]
|
|
8002772: 685a ldr r2, [r3, #4]
|
|
8002774: 687b ldr r3, [r7, #4]
|
|
8002776: 639a str r2, [r3, #56] ; 0x38
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8002778: 687b ldr r3, [r7, #4]
|
|
800277a: 697a ldr r2, [r7, #20]
|
|
800277c: 621a str r2, [r3, #32]
|
|
}
|
|
800277e: bf00 nop
|
|
8002780: 371c adds r7, #28
|
|
8002782: 46bd mov sp, r7
|
|
8002784: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002788: 4770 bx lr
|
|
800278a: bf00 nop
|
|
800278c: 40012c00 .word 0x40012c00
|
|
8002790: 40014000 .word 0x40014000
|
|
8002794: 40014400 .word 0x40014400
|
|
8002798: 40014800 .word 0x40014800
|
|
|
|
0800279c <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800279c: b480 push {r7}
|
|
800279e: b087 sub sp, #28
|
|
80027a0: af00 add r7, sp, #0
|
|
80027a2: 6078 str r0, [r7, #4]
|
|
80027a4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
80027a6: 687b ldr r3, [r7, #4]
|
|
80027a8: 6a1b ldr r3, [r3, #32]
|
|
80027aa: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
80027ac: 687b ldr r3, [r7, #4]
|
|
80027ae: 6a1b ldr r3, [r3, #32]
|
|
80027b0: f423 7280 bic.w r2, r3, #256 ; 0x100
|
|
80027b4: 687b ldr r3, [r7, #4]
|
|
80027b6: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80027b8: 687b ldr r3, [r7, #4]
|
|
80027ba: 685b ldr r3, [r3, #4]
|
|
80027bc: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
80027be: 687b ldr r3, [r7, #4]
|
|
80027c0: 69db ldr r3, [r3, #28]
|
|
80027c2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
80027c4: 68fb ldr r3, [r7, #12]
|
|
80027c6: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
80027ca: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
80027ce: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
80027d0: 68fb ldr r3, [r7, #12]
|
|
80027d2: f023 0303 bic.w r3, r3, #3
|
|
80027d6: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
80027d8: 683b ldr r3, [r7, #0]
|
|
80027da: 681b ldr r3, [r3, #0]
|
|
80027dc: 68fa ldr r2, [r7, #12]
|
|
80027de: 4313 orrs r3, r2
|
|
80027e0: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
80027e2: 697b ldr r3, [r7, #20]
|
|
80027e4: f423 7300 bic.w r3, r3, #512 ; 0x200
|
|
80027e8: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
80027ea: 683b ldr r3, [r7, #0]
|
|
80027ec: 689b ldr r3, [r3, #8]
|
|
80027ee: 021b lsls r3, r3, #8
|
|
80027f0: 697a ldr r2, [r7, #20]
|
|
80027f2: 4313 orrs r3, r2
|
|
80027f4: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
80027f6: 687b ldr r3, [r7, #4]
|
|
80027f8: 4a23 ldr r2, [pc, #140] ; (8002888 <TIM_OC3_SetConfig+0xec>)
|
|
80027fa: 4293 cmp r3, r2
|
|
80027fc: d10d bne.n 800281a <TIM_OC3_SetConfig+0x7e>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
80027fe: 697b ldr r3, [r7, #20]
|
|
8002800: f423 6300 bic.w r3, r3, #2048 ; 0x800
|
|
8002804: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
8002806: 683b ldr r3, [r7, #0]
|
|
8002808: 68db ldr r3, [r3, #12]
|
|
800280a: 021b lsls r3, r3, #8
|
|
800280c: 697a ldr r2, [r7, #20]
|
|
800280e: 4313 orrs r3, r2
|
|
8002810: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
8002812: 697b ldr r3, [r7, #20]
|
|
8002814: f423 6380 bic.w r3, r3, #1024 ; 0x400
|
|
8002818: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
#if defined(TIM_CR2_OIS3)
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800281a: 687b ldr r3, [r7, #4]
|
|
800281c: 4a1a ldr r2, [pc, #104] ; (8002888 <TIM_OC3_SetConfig+0xec>)
|
|
800281e: 4293 cmp r3, r2
|
|
8002820: d00b beq.n 800283a <TIM_OC3_SetConfig+0x9e>
|
|
8002822: 687b ldr r3, [r7, #4]
|
|
8002824: 4a19 ldr r2, [pc, #100] ; (800288c <TIM_OC3_SetConfig+0xf0>)
|
|
8002826: 4293 cmp r3, r2
|
|
8002828: d007 beq.n 800283a <TIM_OC3_SetConfig+0x9e>
|
|
800282a: 687b ldr r3, [r7, #4]
|
|
800282c: 4a18 ldr r2, [pc, #96] ; (8002890 <TIM_OC3_SetConfig+0xf4>)
|
|
800282e: 4293 cmp r3, r2
|
|
8002830: d003 beq.n 800283a <TIM_OC3_SetConfig+0x9e>
|
|
8002832: 687b ldr r3, [r7, #4]
|
|
8002834: 4a17 ldr r2, [pc, #92] ; (8002894 <TIM_OC3_SetConfig+0xf8>)
|
|
8002836: 4293 cmp r3, r2
|
|
8002838: d113 bne.n 8002862 <TIM_OC3_SetConfig+0xc6>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
800283a: 693b ldr r3, [r7, #16]
|
|
800283c: f423 5380 bic.w r3, r3, #4096 ; 0x1000
|
|
8002840: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
8002842: 693b ldr r3, [r7, #16]
|
|
8002844: f423 5300 bic.w r3, r3, #8192 ; 0x2000
|
|
8002848: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
800284a: 683b ldr r3, [r7, #0]
|
|
800284c: 695b ldr r3, [r3, #20]
|
|
800284e: 011b lsls r3, r3, #4
|
|
8002850: 693a ldr r2, [r7, #16]
|
|
8002852: 4313 orrs r3, r2
|
|
8002854: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
8002856: 683b ldr r3, [r7, #0]
|
|
8002858: 699b ldr r3, [r3, #24]
|
|
800285a: 011b lsls r3, r3, #4
|
|
800285c: 693a ldr r2, [r7, #16]
|
|
800285e: 4313 orrs r3, r2
|
|
8002860: 613b str r3, [r7, #16]
|
|
}
|
|
#endif /* TIM_CR2_OIS3 */
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8002862: 687b ldr r3, [r7, #4]
|
|
8002864: 693a ldr r2, [r7, #16]
|
|
8002866: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8002868: 687b ldr r3, [r7, #4]
|
|
800286a: 68fa ldr r2, [r7, #12]
|
|
800286c: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
800286e: 683b ldr r3, [r7, #0]
|
|
8002870: 685a ldr r2, [r3, #4]
|
|
8002872: 687b ldr r3, [r7, #4]
|
|
8002874: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8002876: 687b ldr r3, [r7, #4]
|
|
8002878: 697a ldr r2, [r7, #20]
|
|
800287a: 621a str r2, [r3, #32]
|
|
}
|
|
800287c: bf00 nop
|
|
800287e: 371c adds r7, #28
|
|
8002880: 46bd mov sp, r7
|
|
8002882: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002886: 4770 bx lr
|
|
8002888: 40012c00 .word 0x40012c00
|
|
800288c: 40014000 .word 0x40014000
|
|
8002890: 40014400 .word 0x40014400
|
|
8002894: 40014800 .word 0x40014800
|
|
|
|
08002898 <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8002898: b480 push {r7}
|
|
800289a: b087 sub sp, #28
|
|
800289c: af00 add r7, sp, #0
|
|
800289e: 6078 str r0, [r7, #4]
|
|
80028a0: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
80028a2: 687b ldr r3, [r7, #4]
|
|
80028a4: 6a1b ldr r3, [r3, #32]
|
|
80028a6: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
80028a8: 687b ldr r3, [r7, #4]
|
|
80028aa: 6a1b ldr r3, [r3, #32]
|
|
80028ac: f423 5280 bic.w r2, r3, #4096 ; 0x1000
|
|
80028b0: 687b ldr r3, [r7, #4]
|
|
80028b2: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80028b4: 687b ldr r3, [r7, #4]
|
|
80028b6: 685b ldr r3, [r3, #4]
|
|
80028b8: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
80028ba: 687b ldr r3, [r7, #4]
|
|
80028bc: 69db ldr r3, [r3, #28]
|
|
80028be: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
80028c0: 68fb ldr r3, [r7, #12]
|
|
80028c2: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
|
|
80028c6: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
|
|
80028ca: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
80028cc: 68fb ldr r3, [r7, #12]
|
|
80028ce: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
80028d2: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
80028d4: 683b ldr r3, [r7, #0]
|
|
80028d6: 681b ldr r3, [r3, #0]
|
|
80028d8: 021b lsls r3, r3, #8
|
|
80028da: 68fa ldr r2, [r7, #12]
|
|
80028dc: 4313 orrs r3, r2
|
|
80028de: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
80028e0: 693b ldr r3, [r7, #16]
|
|
80028e2: f423 5300 bic.w r3, r3, #8192 ; 0x2000
|
|
80028e6: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
80028e8: 683b ldr r3, [r7, #0]
|
|
80028ea: 689b ldr r3, [r3, #8]
|
|
80028ec: 031b lsls r3, r3, #12
|
|
80028ee: 693a ldr r2, [r7, #16]
|
|
80028f0: 4313 orrs r3, r2
|
|
80028f2: 613b str r3, [r7, #16]
|
|
|
|
#if defined(TIM_CR2_OIS4)
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
80028f4: 687b ldr r3, [r7, #4]
|
|
80028f6: 4a16 ldr r2, [pc, #88] ; (8002950 <TIM_OC4_SetConfig+0xb8>)
|
|
80028f8: 4293 cmp r3, r2
|
|
80028fa: d00b beq.n 8002914 <TIM_OC4_SetConfig+0x7c>
|
|
80028fc: 687b ldr r3, [r7, #4]
|
|
80028fe: 4a15 ldr r2, [pc, #84] ; (8002954 <TIM_OC4_SetConfig+0xbc>)
|
|
8002900: 4293 cmp r3, r2
|
|
8002902: d007 beq.n 8002914 <TIM_OC4_SetConfig+0x7c>
|
|
8002904: 687b ldr r3, [r7, #4]
|
|
8002906: 4a14 ldr r2, [pc, #80] ; (8002958 <TIM_OC4_SetConfig+0xc0>)
|
|
8002908: 4293 cmp r3, r2
|
|
800290a: d003 beq.n 8002914 <TIM_OC4_SetConfig+0x7c>
|
|
800290c: 687b ldr r3, [r7, #4]
|
|
800290e: 4a13 ldr r2, [pc, #76] ; (800295c <TIM_OC4_SetConfig+0xc4>)
|
|
8002910: 4293 cmp r3, r2
|
|
8002912: d109 bne.n 8002928 <TIM_OC4_SetConfig+0x90>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
8002914: 697b ldr r3, [r7, #20]
|
|
8002916: f423 4380 bic.w r3, r3, #16384 ; 0x4000
|
|
800291a: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
800291c: 683b ldr r3, [r7, #0]
|
|
800291e: 695b ldr r3, [r3, #20]
|
|
8002920: 019b lsls r3, r3, #6
|
|
8002922: 697a ldr r2, [r7, #20]
|
|
8002924: 4313 orrs r3, r2
|
|
8002926: 617b str r3, [r7, #20]
|
|
}
|
|
#endif /* TIM_CR2_OIS4 */
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8002928: 687b ldr r3, [r7, #4]
|
|
800292a: 697a ldr r2, [r7, #20]
|
|
800292c: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
800292e: 687b ldr r3, [r7, #4]
|
|
8002930: 68fa ldr r2, [r7, #12]
|
|
8002932: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
8002934: 683b ldr r3, [r7, #0]
|
|
8002936: 685a ldr r2, [r3, #4]
|
|
8002938: 687b ldr r3, [r7, #4]
|
|
800293a: 641a str r2, [r3, #64] ; 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800293c: 687b ldr r3, [r7, #4]
|
|
800293e: 693a ldr r2, [r7, #16]
|
|
8002940: 621a str r2, [r3, #32]
|
|
}
|
|
8002942: bf00 nop
|
|
8002944: 371c adds r7, #28
|
|
8002946: 46bd mov sp, r7
|
|
8002948: f85d 7b04 ldr.w r7, [sp], #4
|
|
800294c: 4770 bx lr
|
|
800294e: bf00 nop
|
|
8002950: 40012c00 .word 0x40012c00
|
|
8002954: 40014000 .word 0x40014000
|
|
8002958: 40014400 .word 0x40014400
|
|
800295c: 40014800 .word 0x40014800
|
|
|
|
08002960 <TIM_OC5_SetConfig>:
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8002960: b480 push {r7}
|
|
8002962: b087 sub sp, #28
|
|
8002964: af00 add r7, sp, #0
|
|
8002966: 6078 str r0, [r7, #4]
|
|
8002968: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800296a: 687b ldr r3, [r7, #4]
|
|
800296c: 6a1b ldr r3, [r3, #32]
|
|
800296e: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC5E;
|
|
8002970: 687b ldr r3, [r7, #4]
|
|
8002972: 6a1b ldr r3, [r3, #32]
|
|
8002974: f423 3280 bic.w r2, r3, #65536 ; 0x10000
|
|
8002978: 687b ldr r3, [r7, #4]
|
|
800297a: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800297c: 687b ldr r3, [r7, #4]
|
|
800297e: 685b ldr r3, [r3, #4]
|
|
8002980: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
8002982: 687b ldr r3, [r7, #4]
|
|
8002984: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8002986: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC5M);
|
|
8002988: 68fb ldr r3, [r7, #12]
|
|
800298a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
800298e: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
8002992: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8002994: 683b ldr r3, [r7, #0]
|
|
8002996: 681b ldr r3, [r3, #0]
|
|
8002998: 68fa ldr r2, [r7, #12]
|
|
800299a: 4313 orrs r3, r2
|
|
800299c: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC5P;
|
|
800299e: 693b ldr r3, [r7, #16]
|
|
80029a0: f423 3300 bic.w r3, r3, #131072 ; 0x20000
|
|
80029a4: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 16U);
|
|
80029a6: 683b ldr r3, [r7, #0]
|
|
80029a8: 689b ldr r3, [r3, #8]
|
|
80029aa: 041b lsls r3, r3, #16
|
|
80029ac: 693a ldr r2, [r7, #16]
|
|
80029ae: 4313 orrs r3, r2
|
|
80029b0: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
80029b2: 687b ldr r3, [r7, #4]
|
|
80029b4: 4a15 ldr r2, [pc, #84] ; (8002a0c <TIM_OC5_SetConfig+0xac>)
|
|
80029b6: 4293 cmp r3, r2
|
|
80029b8: d00b beq.n 80029d2 <TIM_OC5_SetConfig+0x72>
|
|
80029ba: 687b ldr r3, [r7, #4]
|
|
80029bc: 4a14 ldr r2, [pc, #80] ; (8002a10 <TIM_OC5_SetConfig+0xb0>)
|
|
80029be: 4293 cmp r3, r2
|
|
80029c0: d007 beq.n 80029d2 <TIM_OC5_SetConfig+0x72>
|
|
80029c2: 687b ldr r3, [r7, #4]
|
|
80029c4: 4a13 ldr r2, [pc, #76] ; (8002a14 <TIM_OC5_SetConfig+0xb4>)
|
|
80029c6: 4293 cmp r3, r2
|
|
80029c8: d003 beq.n 80029d2 <TIM_OC5_SetConfig+0x72>
|
|
80029ca: 687b ldr r3, [r7, #4]
|
|
80029cc: 4a12 ldr r2, [pc, #72] ; (8002a18 <TIM_OC5_SetConfig+0xb8>)
|
|
80029ce: 4293 cmp r3, r2
|
|
80029d0: d109 bne.n 80029e6 <TIM_OC5_SetConfig+0x86>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS5;
|
|
80029d2: 697b ldr r3, [r7, #20]
|
|
80029d4: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
80029d8: 617b str r3, [r7, #20]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 8U);
|
|
80029da: 683b ldr r3, [r7, #0]
|
|
80029dc: 695b ldr r3, [r3, #20]
|
|
80029de: 021b lsls r3, r3, #8
|
|
80029e0: 697a ldr r2, [r7, #20]
|
|
80029e2: 4313 orrs r3, r2
|
|
80029e4: 617b str r3, [r7, #20]
|
|
}
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
80029e6: 687b ldr r3, [r7, #4]
|
|
80029e8: 697a ldr r2, [r7, #20]
|
|
80029ea: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
80029ec: 687b ldr r3, [r7, #4]
|
|
80029ee: 68fa ldr r2, [r7, #12]
|
|
80029f0: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR5 = OC_Config->Pulse;
|
|
80029f2: 683b ldr r3, [r7, #0]
|
|
80029f4: 685a ldr r2, [r3, #4]
|
|
80029f6: 687b ldr r3, [r7, #4]
|
|
80029f8: 659a str r2, [r3, #88] ; 0x58
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
80029fa: 687b ldr r3, [r7, #4]
|
|
80029fc: 693a ldr r2, [r7, #16]
|
|
80029fe: 621a str r2, [r3, #32]
|
|
}
|
|
8002a00: bf00 nop
|
|
8002a02: 371c adds r7, #28
|
|
8002a04: 46bd mov sp, r7
|
|
8002a06: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002a0a: 4770 bx lr
|
|
8002a0c: 40012c00 .word 0x40012c00
|
|
8002a10: 40014000 .word 0x40014000
|
|
8002a14: 40014400 .word 0x40014400
|
|
8002a18: 40014800 .word 0x40014800
|
|
|
|
08002a1c <TIM_OC6_SetConfig>:
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8002a1c: b480 push {r7}
|
|
8002a1e: b087 sub sp, #28
|
|
8002a20: af00 add r7, sp, #0
|
|
8002a22: 6078 str r0, [r7, #4]
|
|
8002a24: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8002a26: 687b ldr r3, [r7, #4]
|
|
8002a28: 6a1b ldr r3, [r3, #32]
|
|
8002a2a: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC6E;
|
|
8002a2c: 687b ldr r3, [r7, #4]
|
|
8002a2e: 6a1b ldr r3, [r3, #32]
|
|
8002a30: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
|
|
8002a34: 687b ldr r3, [r7, #4]
|
|
8002a36: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8002a38: 687b ldr r3, [r7, #4]
|
|
8002a3a: 685b ldr r3, [r3, #4]
|
|
8002a3c: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
8002a3e: 687b ldr r3, [r7, #4]
|
|
8002a40: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8002a42: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC6M);
|
|
8002a44: 68fb ldr r3, [r7, #12]
|
|
8002a46: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
|
|
8002a4a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
|
|
8002a4e: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8002a50: 683b ldr r3, [r7, #0]
|
|
8002a52: 681b ldr r3, [r3, #0]
|
|
8002a54: 021b lsls r3, r3, #8
|
|
8002a56: 68fa ldr r2, [r7, #12]
|
|
8002a58: 4313 orrs r3, r2
|
|
8002a5a: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
|
|
8002a5c: 693b ldr r3, [r7, #16]
|
|
8002a5e: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
|
|
8002a62: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 20U);
|
|
8002a64: 683b ldr r3, [r7, #0]
|
|
8002a66: 689b ldr r3, [r3, #8]
|
|
8002a68: 051b lsls r3, r3, #20
|
|
8002a6a: 693a ldr r2, [r7, #16]
|
|
8002a6c: 4313 orrs r3, r2
|
|
8002a6e: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8002a70: 687b ldr r3, [r7, #4]
|
|
8002a72: 4a16 ldr r2, [pc, #88] ; (8002acc <TIM_OC6_SetConfig+0xb0>)
|
|
8002a74: 4293 cmp r3, r2
|
|
8002a76: d00b beq.n 8002a90 <TIM_OC6_SetConfig+0x74>
|
|
8002a78: 687b ldr r3, [r7, #4]
|
|
8002a7a: 4a15 ldr r2, [pc, #84] ; (8002ad0 <TIM_OC6_SetConfig+0xb4>)
|
|
8002a7c: 4293 cmp r3, r2
|
|
8002a7e: d007 beq.n 8002a90 <TIM_OC6_SetConfig+0x74>
|
|
8002a80: 687b ldr r3, [r7, #4]
|
|
8002a82: 4a14 ldr r2, [pc, #80] ; (8002ad4 <TIM_OC6_SetConfig+0xb8>)
|
|
8002a84: 4293 cmp r3, r2
|
|
8002a86: d003 beq.n 8002a90 <TIM_OC6_SetConfig+0x74>
|
|
8002a88: 687b ldr r3, [r7, #4]
|
|
8002a8a: 4a13 ldr r2, [pc, #76] ; (8002ad8 <TIM_OC6_SetConfig+0xbc>)
|
|
8002a8c: 4293 cmp r3, r2
|
|
8002a8e: d109 bne.n 8002aa4 <TIM_OC6_SetConfig+0x88>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS6;
|
|
8002a90: 697b ldr r3, [r7, #20]
|
|
8002a92: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
8002a96: 617b str r3, [r7, #20]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 10U);
|
|
8002a98: 683b ldr r3, [r7, #0]
|
|
8002a9a: 695b ldr r3, [r3, #20]
|
|
8002a9c: 029b lsls r3, r3, #10
|
|
8002a9e: 697a ldr r2, [r7, #20]
|
|
8002aa0: 4313 orrs r3, r2
|
|
8002aa2: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8002aa4: 687b ldr r3, [r7, #4]
|
|
8002aa6: 697a ldr r2, [r7, #20]
|
|
8002aa8: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
8002aaa: 687b ldr r3, [r7, #4]
|
|
8002aac: 68fa ldr r2, [r7, #12]
|
|
8002aae: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR6 = OC_Config->Pulse;
|
|
8002ab0: 683b ldr r3, [r7, #0]
|
|
8002ab2: 685a ldr r2, [r3, #4]
|
|
8002ab4: 687b ldr r3, [r7, #4]
|
|
8002ab6: 65da str r2, [r3, #92] ; 0x5c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8002ab8: 687b ldr r3, [r7, #4]
|
|
8002aba: 693a ldr r2, [r7, #16]
|
|
8002abc: 621a str r2, [r3, #32]
|
|
}
|
|
8002abe: bf00 nop
|
|
8002ac0: 371c adds r7, #28
|
|
8002ac2: 46bd mov sp, r7
|
|
8002ac4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002ac8: 4770 bx lr
|
|
8002aca: bf00 nop
|
|
8002acc: 40012c00 .word 0x40012c00
|
|
8002ad0: 40014000 .word 0x40014000
|
|
8002ad4: 40014400 .word 0x40014400
|
|
8002ad8: 40014800 .word 0x40014800
|
|
|
|
08002adc <TIM_CCxChannelCmd>:
|
|
* @param ChannelState specifies the TIM Channel CCxE bit new state.
|
|
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
|
|
* @retval None
|
|
*/
|
|
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
|
|
{
|
|
8002adc: b480 push {r7}
|
|
8002ade: b087 sub sp, #28
|
|
8002ae0: af00 add r7, sp, #0
|
|
8002ae2: 60f8 str r0, [r7, #12]
|
|
8002ae4: 60b9 str r1, [r7, #8]
|
|
8002ae6: 607a str r2, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
|
|
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
|
|
8002ae8: 68bb ldr r3, [r7, #8]
|
|
8002aea: f003 031f and.w r3, r3, #31
|
|
8002aee: 2201 movs r2, #1
|
|
8002af0: fa02 f303 lsl.w r3, r2, r3
|
|
8002af4: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the CCxE Bit */
|
|
TIMx->CCER &= ~tmp;
|
|
8002af6: 68fb ldr r3, [r7, #12]
|
|
8002af8: 6a1a ldr r2, [r3, #32]
|
|
8002afa: 697b ldr r3, [r7, #20]
|
|
8002afc: 43db mvns r3, r3
|
|
8002afe: 401a ands r2, r3
|
|
8002b00: 68fb ldr r3, [r7, #12]
|
|
8002b02: 621a str r2, [r3, #32]
|
|
|
|
/* Set or reset the CCxE Bit */
|
|
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
|
8002b04: 68fb ldr r3, [r7, #12]
|
|
8002b06: 6a1a ldr r2, [r3, #32]
|
|
8002b08: 68bb ldr r3, [r7, #8]
|
|
8002b0a: f003 031f and.w r3, r3, #31
|
|
8002b0e: 6879 ldr r1, [r7, #4]
|
|
8002b10: fa01 f303 lsl.w r3, r1, r3
|
|
8002b14: 431a orrs r2, r3
|
|
8002b16: 68fb ldr r3, [r7, #12]
|
|
8002b18: 621a str r2, [r3, #32]
|
|
}
|
|
8002b1a: bf00 nop
|
|
8002b1c: 371c adds r7, #28
|
|
8002b1e: 46bd mov sp, r7
|
|
8002b20: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002b24: 4770 bx lr
|
|
...
|
|
|
|
08002b28 <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
8002b28: b480 push {r7}
|
|
8002b2a: b085 sub sp, #20
|
|
8002b2c: af00 add r7, sp, #0
|
|
8002b2e: 6078 str r0, [r7, #4]
|
|
8002b30: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8002b32: 687b ldr r3, [r7, #4]
|
|
8002b34: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
8002b38: 2b01 cmp r3, #1
|
|
8002b3a: d101 bne.n 8002b40 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
8002b3c: 2302 movs r3, #2
|
|
8002b3e: e04f b.n 8002be0 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
|
|
8002b40: 687b ldr r3, [r7, #4]
|
|
8002b42: 2201 movs r2, #1
|
|
8002b44: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8002b48: 687b ldr r3, [r7, #4]
|
|
8002b4a: 2202 movs r2, #2
|
|
8002b4c: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
8002b50: 687b ldr r3, [r7, #4]
|
|
8002b52: 681b ldr r3, [r3, #0]
|
|
8002b54: 685b ldr r3, [r3, #4]
|
|
8002b56: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8002b58: 687b ldr r3, [r7, #4]
|
|
8002b5a: 681b ldr r3, [r3, #0]
|
|
8002b5c: 689b ldr r3, [r3, #8]
|
|
8002b5e: 60bb str r3, [r7, #8]
|
|
|
|
#if defined(TIM_CR2_MMS2)
|
|
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
|
|
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
|
|
8002b60: 687b ldr r3, [r7, #4]
|
|
8002b62: 681b ldr r3, [r3, #0]
|
|
8002b64: 4a21 ldr r2, [pc, #132] ; (8002bec <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
|
|
8002b66: 4293 cmp r3, r2
|
|
8002b68: d108 bne.n 8002b7c <HAL_TIMEx_MasterConfigSynchronization+0x54>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
|
|
|
|
/* Clear the MMS2 bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS2;
|
|
8002b6a: 68fb ldr r3, [r7, #12]
|
|
8002b6c: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
|
|
8002b70: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO2 source*/
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
|
|
8002b72: 683b ldr r3, [r7, #0]
|
|
8002b74: 685b ldr r3, [r3, #4]
|
|
8002b76: 68fa ldr r2, [r7, #12]
|
|
8002b78: 4313 orrs r3, r2
|
|
8002b7a: 60fb str r3, [r7, #12]
|
|
}
|
|
#endif /* TIM_CR2_MMS2 */
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
8002b7c: 68fb ldr r3, [r7, #12]
|
|
8002b7e: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
8002b82: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8002b84: 683b ldr r3, [r7, #0]
|
|
8002b86: 681b ldr r3, [r3, #0]
|
|
8002b88: 68fa ldr r2, [r7, #12]
|
|
8002b8a: 4313 orrs r3, r2
|
|
8002b8c: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
8002b8e: 687b ldr r3, [r7, #4]
|
|
8002b90: 681b ldr r3, [r3, #0]
|
|
8002b92: 68fa ldr r2, [r7, #12]
|
|
8002b94: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8002b96: 687b ldr r3, [r7, #4]
|
|
8002b98: 681b ldr r3, [r3, #0]
|
|
8002b9a: 4a14 ldr r2, [pc, #80] ; (8002bec <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
|
|
8002b9c: 4293 cmp r3, r2
|
|
8002b9e: d009 beq.n 8002bb4 <HAL_TIMEx_MasterConfigSynchronization+0x8c>
|
|
8002ba0: 687b ldr r3, [r7, #4]
|
|
8002ba2: 681b ldr r3, [r3, #0]
|
|
8002ba4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
8002ba8: d004 beq.n 8002bb4 <HAL_TIMEx_MasterConfigSynchronization+0x8c>
|
|
8002baa: 687b ldr r3, [r7, #4]
|
|
8002bac: 681b ldr r3, [r3, #0]
|
|
8002bae: 4a10 ldr r2, [pc, #64] ; (8002bf0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>)
|
|
8002bb0: 4293 cmp r3, r2
|
|
8002bb2: d10c bne.n 8002bce <HAL_TIMEx_MasterConfigSynchronization+0xa6>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
8002bb4: 68bb ldr r3, [r7, #8]
|
|
8002bb6: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
8002bba: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
8002bbc: 683b ldr r3, [r7, #0]
|
|
8002bbe: 689b ldr r3, [r3, #8]
|
|
8002bc0: 68ba ldr r2, [r7, #8]
|
|
8002bc2: 4313 orrs r3, r2
|
|
8002bc4: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8002bc6: 687b ldr r3, [r7, #4]
|
|
8002bc8: 681b ldr r3, [r3, #0]
|
|
8002bca: 68ba ldr r2, [r7, #8]
|
|
8002bcc: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8002bce: 687b ldr r3, [r7, #4]
|
|
8002bd0: 2201 movs r2, #1
|
|
8002bd2: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8002bd6: 687b ldr r3, [r7, #4]
|
|
8002bd8: 2200 movs r2, #0
|
|
8002bda: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return HAL_OK;
|
|
8002bde: 2300 movs r3, #0
|
|
}
|
|
8002be0: 4618 mov r0, r3
|
|
8002be2: 3714 adds r7, #20
|
|
8002be4: 46bd mov sp, r7
|
|
8002be6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002bea: 4770 bx lr
|
|
8002bec: 40012c00 .word 0x40012c00
|
|
8002bf0: 40014000 .word 0x40014000
|
|
|
|
08002bf4 <__libc_init_array>:
|
|
8002bf4: b570 push {r4, r5, r6, lr}
|
|
8002bf6: 4d0d ldr r5, [pc, #52] ; (8002c2c <__libc_init_array+0x38>)
|
|
8002bf8: 4c0d ldr r4, [pc, #52] ; (8002c30 <__libc_init_array+0x3c>)
|
|
8002bfa: 1b64 subs r4, r4, r5
|
|
8002bfc: 10a4 asrs r4, r4, #2
|
|
8002bfe: 2600 movs r6, #0
|
|
8002c00: 42a6 cmp r6, r4
|
|
8002c02: d109 bne.n 8002c18 <__libc_init_array+0x24>
|
|
8002c04: 4d0b ldr r5, [pc, #44] ; (8002c34 <__libc_init_array+0x40>)
|
|
8002c06: 4c0c ldr r4, [pc, #48] ; (8002c38 <__libc_init_array+0x44>)
|
|
8002c08: f000 f820 bl 8002c4c <_init>
|
|
8002c0c: 1b64 subs r4, r4, r5
|
|
8002c0e: 10a4 asrs r4, r4, #2
|
|
8002c10: 2600 movs r6, #0
|
|
8002c12: 42a6 cmp r6, r4
|
|
8002c14: d105 bne.n 8002c22 <__libc_init_array+0x2e>
|
|
8002c16: bd70 pop {r4, r5, r6, pc}
|
|
8002c18: f855 3b04 ldr.w r3, [r5], #4
|
|
8002c1c: 4798 blx r3
|
|
8002c1e: 3601 adds r6, #1
|
|
8002c20: e7ee b.n 8002c00 <__libc_init_array+0xc>
|
|
8002c22: f855 3b04 ldr.w r3, [r5], #4
|
|
8002c26: 4798 blx r3
|
|
8002c28: 3601 adds r6, #1
|
|
8002c2a: e7f2 b.n 8002c12 <__libc_init_array+0x1e>
|
|
8002c2c: 08002c94 .word 0x08002c94
|
|
8002c30: 08002c94 .word 0x08002c94
|
|
8002c34: 08002c94 .word 0x08002c94
|
|
8002c38: 08002c98 .word 0x08002c98
|
|
|
|
08002c3c <memset>:
|
|
8002c3c: 4402 add r2, r0
|
|
8002c3e: 4603 mov r3, r0
|
|
8002c40: 4293 cmp r3, r2
|
|
8002c42: d100 bne.n 8002c46 <memset+0xa>
|
|
8002c44: 4770 bx lr
|
|
8002c46: f803 1b01 strb.w r1, [r3], #1
|
|
8002c4a: e7f9 b.n 8002c40 <memset+0x4>
|
|
|
|
08002c4c <_init>:
|
|
8002c4c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8002c4e: bf00 nop
|
|
8002c50: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8002c52: bc08 pop {r3}
|
|
8002c54: 469e mov lr, r3
|
|
8002c56: 4770 bx lr
|
|
|
|
08002c58 <_fini>:
|
|
8002c58: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8002c5a: bf00 nop
|
|
8002c5c: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8002c5e: bc08 pop {r3}
|
|
8002c60: 469e mov lr, r3
|
|
8002c62: 4770 bx lr
|